IP Library Granted Patent US 9,478,606
Granted Patent B2
US 9,478,606 · App. 14/622,309 · Granted Oct 25, 2016

SiC transient voltage suppressor

Inventors: Dumitru Sdrulla (Bend, OR); Bruce Odekirk (Bend, OR); Cecil Kent Walters (Scottsdale, AZ)
Assignee: Microsemi Corporation
H01L29/0626H01L29/0619H01L29/1608H01L29/36H01L29/872H01L29/6603H01L29/861H01L29/8618
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Quick Facts
Patent No.
US 9,478,606
App. No.
14/622,309
Granted
Oct 25, 2016
Kind
B2
Abstract

A high power, high current Unidirectional Transient Voltage Suppressor, formed on SiC starting material is disclosed. The device is structured to avalanche uniformly across the entire central part (active area) such that very high currents can flow while the device is reversely biased. Forcing the device to avalanche uniformly across designated areas is achieved in different ways but consistently in concept, by creating high electric fields where the device is supposed to avalanche (namely the active area) and by relaxing the electric field across the edge of the structure (namely in the termination), which in all embodiments meets the conditions for an increased reliability under harsh environments.

Claims (69)

1. A transient voltage suppressor, comprising:

a silicon carbide (SiC) substrate of a first dopant type and a first doping concentration;

a backside conductive contact on a backside of the substrate;

an epitaxial SiC layer of the first dopant type and a second doping concentration less than the first doping concentration on the substrate;

a central active area including one or more regions of a second dopant type opposite the first dopant type forming a PN junction in the epitaxial layer;

a frontside conductive contact on an upper side of the epitaxial SiC layer coupled to the one or more regions of the second dopant type; and

a peripheral termination area surrounding the central active area and including a termination structure arranged to suppress electric field and avalanche around the central contact area;

the central active area being structured to avalanche within the active area under a voltage condition applied across the conductive contacts that exceeds a predetermined breakdown voltage in the central active area that is less than a breakdown voltage of the peripheral termination area;

in which:

the epitaxial SiC layer has an upper surface;

the central active area includes an array of spaced-apart trenches each having a bottom spaced below the upper surface with first implants of the second dopant type in the bottom of each trench; and

the peripheral termination area includes an array of second implants of the second dopant type subjacent the upper surface of the epitaxial SiC layer;

the first implants extending to a depth in the epitaxial SiC layer greater than a depth of the second implants so as to thereby provide the lower breakdown voltage in the central active area than a breakdown voltage in the peripheral termination area.

2. A transient voltage suppressor according to claim 1 capable of a clamping voltage greater than 500V.

3. A transient voltage suppressor according to claim 1 capable of a clamping voltage greater than 100V.

4. A transient voltage suppressor according to claim 1 in which the frontside conductive contact includes a Schottky metal layer.

5. A transient voltage suppressor, comprising:

a silicon carbide (SiC) substrate of a first dopant type and a first doping concentration;

a backside conductive contact on a backside of the substrate;

an epitaxial SiC layer of the first dopant type and a second doping concentration less than the first doping concentration on the substrate;

a central active area including one or more regions of a second dopant type opposite the first dopant type forming a PN junction in the epitaxial layer;

a frontside conductive contact on an upper side of the epitaxial SiC layer coupled to the one or more regions of the second dopant type; and

a peripheral termination area surrounding the central active area and including a termination structure arranged to suppress electric field and avalanche around the central contact area;

the central active area being structured to avalanche within the active area under a voltage condition applied across the conductive contacts that exceeds a predetermined breakdown voltage in the central active area that is less than a breakdown voltage of the peripheral termination area;

in which:

the epitaxial SiC layer includes a first epitaxial sublayer of the second doping concentration and a second epitaxial sublayer of a third doping concentration greater than the second doping concentration atop the first epitaxial sublayer, each epitaxial sublayer having an upper surface;

the central active area being formed subjacent the upper surface of the second epitaxial sublayer and the peripheral termination area being formed subjacent the upper surface of the first epitaxial sublayer.

6. A transient voltage suppressor according to claim 5 in which the frontside conductive contact includes a Schottky metal layer.

7. A transient voltage suppressor, comprising:

a silicon carbide (SiC) substrate of a first dopant type and a first doping concentration;

a backside conductive contact on a backside of the substrate;

an epitaxial SiC layer of the first dopant type and a second doping concentration less than the first doping concentration on the substrate;

a central active area including one or more regions of a second dopant type opposite the first dopant type forming a PN junction in the epitaxial layer;

a frontside conductive contact on an upper side of the epitaxial SiC layer coupled to the one or more regions of the second dopant type; and

a peripheral termination area surrounding the central active area and including a termination structure arranged to suppress electric field and avalanche around the central contact area;

the central active area being structured to avalanche within the active area under a voltage condition applied across the conductive contacts that exceeds a predetermined breakdown voltage in the central active area that is less than a breakdown voltage of the peripheral termination area;

in which:

the epitaxial SiC layer includes a first epitaxial sublayer of the second doping concentration and a second epitaxial sublayer of a third doping concentration between the first epitaxial sublayer and the substrate, the third doping concentration less than the first doping concentration of the substrate and greater than the second doping concentration.

8. A transient voltage suppressor according to claim 7 in which the frontside conductive contact includes a Schottky metal layer.

9. A transient voltage suppressor, comprising:

a silicon carbide (SiC) substrate of a first dopant type and a first doping concentration;

a backside conductive contact on a backside of the substrate;

an epitaxial SiC layer of the first dopant type and a second doping concentration less than the first doping concentration on the substrate;

a central active area including one or more regions of a second dopant type opposite the first dopant type forming a PN junction in the epitaxial layer;

a frontside conductive contact on an upper side of the epitaxial SiC layer coupled to the one or more regions of the second dopant type; and

a peripheral termination area surrounding the central active area and including a termination structure arranged to suppress electric field and avalanche around the central contact area;

the central active area being structured to avalanche within the active area under a voltage condition applied across the conductive contacts that exceeds a predetermined breakdown voltage in the central active area that is less than a breakdown voltage of the peripheral termination area;

in which the second doping concentration in the epitaxial SiC layer has a graded dopant profile spanning an interface between the substrate and the epitaxial SiC layer.

10. A transient voltage suppressor according to claim 9 in which the frontside conductive contact includes a Schottky metal layer.

11. A transient voltage suppressor, comprising:

a silicon carbide (SiC) substrate of a first dopant type and a first doping concentration;

a backside conductive contact on a backside of the substrate;

an epitaxial SiC layer of the first dopant type and a second doping concentration less than the first doping concentration on the substrate;

a central active area including a region of a second dopant type opposite the first dopant type forming a PN junction in the epitaxial layer;

a frontside conductive contact on an upper side of the epitaxial SiC layer coupled to the region of the second dopant type; and

a peripheral termination area surrounding the central active area and including a termination structure arranged to suppress electric field and avalanche around the central contact area;

the central active area being recessed to form a trench having a bottom spaced below the upper side of the epitaxial SiC layer, the region of second dopant type being located below the bottom of the trench so as to avalanche within the active area under a voltage condition applied across the conductive contacts that exceeds a predetermined threshold voltage.

12. A transient voltage suppressor according to claim 11 in which the termination structure includes termination rings of the second dopant type implanted in the epitaxial SiC layer above the bottom of the trench.

13. A transient voltage suppressor, comprising:

a silicon carbide (SiC) substrate of a first dopant type and a first doping concentration;

a backside conductive contact on a backside of the substrate;

an epitaxial SiC layer of the first dopant type and a second doping concentration less than the first doping concentration on the substrate;

a central active area including multiple cellular or stripe regions of a second dopant type opposite the first dopant type, each forming a PN junction in the epitaxial layer ;

a frontside conductive contact on an upper side of the epitaxial SiC layer coupled to each of the regions of the second dopant type; and

a peripheral termination area surrounding the central active area and including a termination structure arranged to suppress electric field and avalanche around the central contact area;

the central active area being structured as an array of the cellular or stripe regions of the second dopant type formed in bottoms of trenches in the epitaxial SiC layer so as to avalanche within the active area under a voltage condition applied across the conductive contacts that exceeds a predetermined threshold voltage.

14. A transient voltage suppressor according to claim 13 in which second regions of the second dopant type are formed on the upper side of the epitaxial SiC layer between the trenches.

15. A transient voltage suppressor according to claim 14 in which the trenches have side walls between the cellular or stripe regions at the bottoms of the trenches and the second regions, the frontside conductive contact extending over the bottoms of the trenches, the side walls and the upper side of the epitaxial SiC layer between the trenches.

16. A transient voltage suppressor according to claim 15 in which the frontside conductive contact includes a Schottky metal layer.

Assignments (16)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 25, 2016
From: WALTERS, CECIL KENT
To: MICROSEMI CORPORATION
Reel/Frame 037576/0332 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2015
From: SDRULLA, DUMITRU; ODEKIRK, BRUCE
To: MICROSEMI CORPORATION
Reel/Frame 034962/0616 →
Continuity (2)
Provisional Application 61939286 · Feb 13, 2014
Related Publication 20160126306A1 · May 5, 2016