Self-timer for sense amplifier in memory device
A self-timer for a sense amplifier in a memory device is disclosed.
1. A circuit for generating a sense amplifier control signal, comprising:
a reference memory cell;
a multiplexer comprising an input and an output, the input coupled to the reference memory cell;
a pre-charge block coupled to the output of the multiplexer;
a timing generator coupled to the output of the multiplexer; and
logic control coupled to the output of the timing generator to generate a sense amplifier control signal that controls a sense amplifier.
2. The circuit of claim 1 , wherein the reference memory cell is a flash memory cell.
3. The circuit of claim 1 , wherein the reference memory cell emulates one or more memory cells in a flash memory array.
4. A circuit for generating a sense amplifier control signal, comprising:
a reference memory cell;
a multiplexer coupled to the reference memory cell;
a pre-charge block coupled to the output of the multiplexer;
a timing generator coupled to the output of the multiplexer; and
logic control coupled to the output of the timing generator to generate a sense amplifier control signal that controls a sense amplifier;
wherein the timing generator comprises a plurality of capacitors.
5. The circuit of claim 4 , wherein the timing generator comprises an inverter.
6. The circuit of claim 5 , wherein the timing generator further comprises a transistor in parallel with the inverter.
7. A method of initiating a sense amplifier operation in a memory system, comprising:
receiving, by an input of a multiplexer, a first current generated by a reference memory cell;
generating, at an output of the multiplexer, a second current in response to the first current;
charging the output of the multiplexer using a pre-charge circuit;
generating, by a timing generator and logic control, a sense amplifier control signal for controlling a sense amplifier in response to the output of the multiplexer.
8. The method of claim 7 , wherein the reference memory cell is a flash memory cell.
9. The method of claim 7 , wherein the reference memory cell emulates one or more memory cells in a flash memory array.
10. A method of initiating a sense amplifier operation in a memory system, comprising:
generating, by a reference memory cell, a current through a node;
charging the node using a pre-charge circuit; and
generating, by a timing generator and logic control, a sense amplifier control signal for controlling a sense amplifier in response to the node;
wherein the timing generator comprises a plurality of capacitors.
11. The method of claim 10 , wherein the timing generator comprises an inverter.
12. The method of claim 11 , wherein the timing generator comprises a transistor in parallel with the inverter.
13. The method of claim 12 , further comprising the step of the transistor equalizing the inverter prior to the generating step.