Message translator
Systems, methods, circuits and computer-readable mediums for a network message translator are disclosed. In an embodiment, a device includes a host processor and a translator. The host processor is configured to process messages and the translator is operable to: receive a first message from the host processor, the first message having a first frame format that is associated with a data time window; translate the first message into a first translated message having a second frame format such that the first translated message includes additional bits based on the second frame format; and sending the first translated message on a bus based on the second frame format such that the first translated message is sent on the bus during the data time window.
1. A device comprising:
a host processor configured to process messages for transmission on a data bus;
a translator coupled to the data bus and configured to:
receive a message frame from the host processor over an interface, the message frame having a first frame format that is configured to be transmitted on the data bus within a data time window at a first data rate;
translate the message frame into a translated message frame having a second frame format, the second frame format including data bits representing a message, sequence bits representing a binary counter to a prevent relay attack, pad bits to fill out the translated message frame and allow bit alignment and security bits to detect if the data bits were modified between transmitting and receiving nodes coupled to the data bus by an unauthorized transmitter coupled to the data bus, the second frame format configured to be transmitted on the data bus within the data time window at a second data rate higher than the first data rate; and
during the data time window, placing the data bits on the data bus, followed by the sequence bits, followed by a first portion of the pad bits, followed by the security bits, followed by a second portion of the pad bits.
2. The device of claim 1 , wherein at least one of the sequence bits and the pad bits are placed on the data bus while at least one of the data bits is being received by the translator from the host processor across the interface.
3. The device of claim 1 , wherein at least one of the security bits and error code bits in the translated message frame are placed on the data bus during an error code time window of the message frame.
4. The device of claim 1 , wherein the data bus is a Controller Area Network (CAN) bus.
5. The device of claim 1 , wherein the device is further configured to:
prior to transmitting the data bits on the data bus:
transfer the data bits to the translator; and
compute, by the translator, the security bits based on the data bits.
6. The device of claim 1 , wherein the translator is integrated with a bus transceiver.
7. The device of claim 1 , wherein the security bits comprise a message authentication code (MAC).
8. A non-transitory, computer-readable storage medium having instructions stored thereon, which, when executed by one or more processors, causes the one or more processors to perform operations comprising:
receiving a message frame from the host processor over an interface, the message frame having a first frame format that is configured to be transmitted on a data bus within a data time window at a first data rate;
translating the message frame into a translated message frame having a second frame format, the second frame format including data bits representing a message, sequence bits representing a binary counter to a prevent relay attack, pad bits to fill out the translated message frame and allow bit alignment and security bits to detect if the data bits were modified between transmitting and receiving nodes coupled to the data bus by an unauthorized transmitter coupled to the data bus, the second frame format configured to be transmitted on the data bus within the data time window at a second data rate higher than the first data rate; and
during the data time window, placing the data bits on the data bus, followed by the sequence bits, followed by a first portion of the pad bits, followed by the security bits, followed by a second portion of the pad bits.
9. The computer-readable storage medium of claim 8 , wherein at least one of the sequence bits and the pad bits are placed on the data bus while at least one of the data bits are being received by the translator from the host processor across the interface.
10. The computer-readable storage medium of claim 8 , wherein at least one of the security bits and error code bits in the translated message frame are placed on the data bus during an error code time window of the message frame.
11. The computer-readable storage medium of claim 8 , wherein the data bus is a Controller Area Network (CAN) bus.
12. The computer-readable storage medium of claim 8 , wherein prior to transmitting the data bits on the data bus:
transferring the data bits to the translator; and
computing, by the translator, the security bits based on the data bits.
13. The computer-readable storage medium of claim 8 , wherein the security bits comprise a message authentication code (MAC).
14. A method comprising:
receiving a message frame from the host processor over an interface, the message frame having a first frame format that is configured to be transmitted on a data bus within a data time window at a first data rate;
translating the message frame into a translated message frame having a second frame format, the second frame format including data bits representing a message, sequence bits representing a binary counter to a prevent relay attack, pad bits to fill out the translated message frame and allow bit alignment and security bits to detect if the data bits were modified between transmitting and receiving nodes coupled to the data bus by an unauthorized transmitter coupled to the data bus, the second frame format configured to be transmitted on the data bus within the data time window at a second data rate higher than the first data rate; and
during the data time window, placing the data bits on the data bus, followed by the sequence bits, followed by a first portion of the pad bits, followed by the security bits, followed by a second portion of the pad bits.
15. The method of claim 14 , wherein the data bus is a Controller Area Network (CAN) bus.
16. The method of claim 14 , wherein the security bits comprise a message authentication code (MAC).
17. The method of claim 14 , wherein at least one of the sequence bits and the pad bits are placed on the data bus while at least one of the data bits are being received by the translator from the host processor across the interface.
18. The method of claim 14 , wherein at least one of the security bits and error code bits in the translated message frame are placed on the data bus during an error code time window of the message frame.
19. The method of claim 14 , further comprising:
transferring the data bits to the translator; and
computing, by the translator, the security bits based on the data bits.
20. The method of claim 19 , further comprising:
caching, by the translator, the data bits; and
synchronizing, by the translator, the data bits in the message frame and translated message frame by matching control fields in the message frame and the translated method frame.