IP Library Granted Patent US 10,873,330
Granted Patent B2
US 10,873,330 · App. 15/209,321 · Granted Dec 22, 2020

Electrode design for electric field measurement system

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Quick Facts
Patent No.
US 10,873,330
App. No.
15/209,321
Granted
Dec 22, 2020
Kind
B2
Abstract

An electrode arrangement for an electric field sensor device with a transmitting electrode and at least one receiving electrode may have a nonconductive substrate having a first conductive layer and a second conductive layer. A first electrode is arranged within the first conductive layer, wherein the first electrode is a receiving electrode of the electric field sensor device, and a second electrode is arranged within the second conductive layer, wherein the second electrode is a transmitting electrode of the electric field sensor device wherein the second electrode covers a larger area than the first electrode and wherein the second electrode is textured to reduce the capacitance between the first and second electrode.

Claims (31)

1. An electrode arrangement for an electric field sensor device, comprising:

a non conductive substrate having a first conductive layer arranged on a first side of the nonconductive substrate and a second conductive layer arranged on a second side of the nonconductive substrate opposite of said first side,

a plurality of receiving electrodes comprising a first set of four receiving electrodes arranged within the first conductive layer such that the four receiving electrodes form a first frame, and

a plurality of electrically insulated transmitting electrodes arranged within the second conductive layer, wherein to generate a quasi-static electric field the electrode arrangement is configured to feed an alternating signal having a frequency of 30-200 kHz to one of the electrically insulated transmitting electrodes in a first mode and in a second mode to feed the same alternating signal having a frequency of 30-200 kHz to the plurality of electrically insulated transmitting electrodes to improve a spatial resolution of the electrode arrangement.

2. The electrode arrangement according to claim 1 , wherein a surface area of the electrically insulated transmitting electrodes and/or the receiving electrodes are textured by a hash or hatched texture.

3. The electrode arrangement according to claim 1 , wherein the entire area of each the electrically insulated transmitting electrode is textured.

4. The electrode arrangement according to claim 3 , wherein the hatched texture forms a grid.

5. The electrode arrangement according to claim 4 , wherein the texture is homogenous.

6. The electrode arrangement according to claim 4 , wherein the hash or hatched texture is formed by a plurality of conductive lines forming a mesh.

7. The electrode arrangement according to claim 6 , wherein the mesh is formed by a first set of parallel arranged conductive lines and a second set of parallel arranged conductive lines.

8. The electrode arrangement according to claim 7 , wherein the first set of parallel arranged conductive lines crosses said second set of parallel arranged conductive lines at an angle of 90 degrees.

9. The electrode arrangement according to claim 7 , wherein the mesh comprises a peripheral conductive line enclosing the mesh.

10. The electrode arrangement according to claim 1 , wherein the receiving electrodes are strip shaped and arranged in parallel.

11. The electrode arrangement according to claim 1 , wherein the electrically insulated transmitting electrodes are strip shaped and arranged in parallel.

12. The electrode arrangement according to claim 1 , wherein the receiving electrodes are strip shaped and arranged in parallel and the electrically insulated transmitting electrodes are strip shaped and arranged in parallel and perpendicular to said receiving electrodes and wherein a width of each electrically insulated transmitting electrode is wider than a width of a receiving electrode.

13. The electrode arrangement according to claim 1 , further comprising a plurality of feeding lines formed in said first conductive layer for electrical connection to said plurality of receiving electrodes.

14. The electrode arrangement according to claim 13 , further comprising a front end analog device coupled with said receiving electrodes through said feeding lines.

15. The electrode arrangement according to claim 14 , wherein the front end analog device comprises a voltage divider for attenuating a signal received through said feeding lines.

16. The electrode arrangement according to claim 15 , wherein the voltage divider comprises a frequency compensation.

17. The electrode arrangement according to claim 1 , wherein the first conductive layer is a top layer of a printed circuit board and wherein the second conductive layer is a bottom layer of a printed circuit board.

18. A printed circuit board comprising an electrode arrangement for an electric field sensor device, comprising:

a non conductive substrate having a first conductive layer arranged on a first side of the nonconductive substrate and a second conductive layer arranged on a second side of the nonconductive substrate opposite of said first side,

a plurality of receiving electrodes comprising a first set of four receiving electrodes arranged within the first conductive layer such that the four receiving electrodes form a first frame, and

a plurality of electrically insulated transmitting electrodes arranged within the second conductive layer, wherein a surface area of each electrically insulated transmitting electrode is textured, and wherein to generate a quasi-static electric field the electrode arrangement is configured in a first mode to feed an alternating signal having a frequency of 30-200 kHz to one of the electrically insulated transmitting electrodes and in a second mode to feed the same alternating signal having a frequency of 30-200 kHz to the plurality of electrically insulated transmitting electrodes to improve a spatial resolution of tire electrode arrangement.

19. A printed circuit board comprising an electrode arrangement for an electric field sensor device, comprising:

a nonconductive substrate having a first conductive layer arranged on a first side of the nonconductive substrate and a second conductive layer arranged on a second side of the nonconductive substrate opposite of said first side,

a plurality of receiving electrodes comprising a first set of four receiving electrodes arranged within the first conductive layer such that the four receiving electrodes form a first frame, and

a plurality of electrically insulated transmitting electrodes arranged within the second conductive layer, wherein a surface area of each electrically insulated transmitting electrode is textured by a hash or hatched texture, wherein the hash or hatched texture is formed by a plurality of conductive lines forming a mesh, wherein the mesh comprises a peripheral conductive line enclosing the mesh, wherein to generate a quasi-static electric field the electrode arrangement is configured in a first mode to feed an alternating signal having a frequency of 30-200 kHz to one of the electrically insulated transmitting electrodes and in a second mode to feed the same alternating signal having a frequency of 30-200 kHz to the plurality of electrically insulated transmitting electrodes to improve a spatial resolution of the electrode arrangement.

20. The printed circuit board according to claim 10 , wherein the mesh is formed by a first set of parallel arranged conductive lines and a second set of parallel arranged conductive lines, wherein the first set of parallel arranged conductive lines crosses said second set of parallel arranged conductive lines at an angle of 90 degrees.

21. The printed circuit board according to claim 19 , wherein the receiving electrodes are strip shaped and arranged in parallel.

22. The printed circuit board according to claim 21 , wherein the electrically insulated transmitting electrodes are strip shaped and arranged in parallel perpendicular to said receiving electrodes.

Assignments (14)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →