Granted Patent B2

US 10,317,978 · App. 15/368,808 · Granted Jun 11, 2019

Inventors: Sebastien Jouin (La Chapelle-Launay, FR); Romain Oddoart (Petit-Mars, FR); Patrice Menard (Saint-Mars-du-Desert, FR); Mickael Le Dily (Carquefou, FR); Thierry Gourbilleau (Le Loroux-Bottereau, FR)

Assignee: Atmel Corporation

G06F1/3243G06F1/3287G06F13/1673Y02D10/152

Abstract

Claims (28)

1. A microcontroller operable in a low-power mode, the microcontroller comprising:

a plurality of I/O connectors;

an I/O controller operable to provide control signals for controlling states of the I/O connectors, wherein the I/O controller is powered off or deactivated during the low-power mode; and

I/O connector state retention logic operable to store states of the control signals so as to maintain the I/O connectors in respective states that existed just prior to the I/O controller becoming powered off or deactivated, wherein the states are maintained while the microcontroller is in the low-power mode.

2. The microcontroller of claim 1 wherein the I/O connectors include at least one of I/O pads or I/O pins.

3. The microcontroller of claim 1 wherein the I/O connector state retention logic includes latches.

4. The microcontroller of claim 3 wherein the latches are SR latches.

5. The microcontroller of claim 3 wherein the latches are operable to be enabled to retain input data values for the I/O connectors even after the microcontroller enters the low power mode.

6. The microcontroller of claim 3 wherein the latches are operable to be enabled to retain output enable values for the I/O connectors even after the microcontroller enters the low power mode.

7. The microcontroller of claim 3 wherein the latches are operable to be enabled to retain drive strength control values for the I/O connectors even after the microcontroller enters the low power mode.

8. The microcontroller of claim 1 wherein the I/O connector state retention logic is operable to retain input data values, output enable values and drive strength control values for the I/O connectors even after the microcontroller enters the low power mode.

9. The microcontroller of claim 8 operable to return to an active mode from the low-power mode, wherein, in the active mode, control of input signals for the input data values, output enable values and drive strength control values returns to the I/O controller.

10. The microcontroller of claim 9 operable to return to the active mode from the low-power mode when an internal counter reaches a predetermined count.

11. The microcontroller of claim 9 operable to return to the active mode from the low-power mode in response to a reset signal.

12. The microcontroller of claim 1 wherein at least some of the control signals for controlling states of the I/O connectors allow the I/O controller to drive a logical 1 or 0 onto the I/O connectors.

13. The microcontroller of claim 1 wherein at least some of the control signals for controlling states of the I/O connectors indicate whether I/O pads are to be used for input or output.

14. The microcontroller of claim 13 wherein if a particular one of the control signals indicates that a particular one of the I/O pads is to be used for output, the particular control signal also enables an output buffer.

15. The microcontroller of claim 1 wherein at least some of the control signals for controlling states of the I/O connectors indicate a drive strength setting.

16. A microcontroller operable in a low-power mode, the microcontroller comprising:

a plurality of I/O connectors;

an I/O controller operable to provide control signals for controlling states of the I/O connectors, wherein the I/O controller is powered off or deactivated during the low-power mode;

I/O connector state retention logic operable to store states of the control signals so as to maintain the I/O connectors in respective states that existed just prior to the I/O controller becoming powered off or deactivated, wherein the states are maintained while the microcontroller is in the low-power mode, thereby executing an I/O connector state retention function;

a power state manager; and

a user interface that, depending on a value stored in a data holding logic element of the user interface, allows either automated I/O connector state retention by the power state manager or user-controlled I/O connector state retention.

17. The microcontroller of claim 16 wherein, if a first value is stored in the data holding logic element, the user interface allows the power state manager to initiate execution of the I/O connector state retention function automatically when the microcontroller enters the low-power mode, and allows release of the I/O connector state retention function automatically when the microcontroller exits the low-power mode.

18. The microcontroller of claim 17 wherein the I/O connector state retention logic includes a plurality of latches each of which is operable to be enabled to latch a respective one of the control signals from the I/O controller.

19. The microcontroller of claim 18 wherein the power state manager is operable to provide a signal to cause the latches to latch the respective control signals when the microcontroller enters the low-power mode.

20. The microcontroller of claim 19 wherein, when the microcontroller exits the low-power mode, the power state manager releases the signal that caused the latches to latch the respective control signals.

Assignments (16)

Continuity (3)