Interconnect structure having tungsten contact copper wiring
Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect structures include one or more electronic devices formed on a substrate. A first interlevel dielectric (ILD) layer is over the one or more electronic devices. The interconnect structure includes a first trench in the first ILD layer. A tungsten contact fills the first trench and is in electrical contact with the one or more electronic devices. A second ILD layer is over the first ILD layer. The interconnect structure includes a second trench in the second ILD layer. Diffusion barrier liners bound all sides of the second trench except at a surface of the tungsten contact. The interconnect structure includes a copper wire filling the second trench, the copper wire in direct contact with the tungsten contact and with the diffusion barrier liners.
1. A method of forming an interconnect structure on a substrate, the substrate including a tungsten contact to one or more electronic devices, the method comprising:
depositing a dielectric material on the substrate;
forming at least one first opening in the dielectric material to expose the tungsten contact,
wherein the tungsten contact has a tungsten region including an upper surface;
depositing a diffusion barrier liner in the at least one first opening, wherein the diffusion barrier liner is selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), ruthenium (Ru), ruthenium nitride (RuN), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), and titanium (Ti);
forming a second opening in the diffusion barrier liner to partially uncover the tungsten contact, wherein a portion of the diffusion barrier liner is in direct contact with the upper surface of the tungsten region after forming the second opening,
filling at least the first opening and the second opening with copper; and
planarizing a top surface of the interconnect structure.
2. The method of claim 1 , wherein the one or more electronic devices are selected from the group consisting of: capacitors, diodes, resistors, transistors, memory cells, varactors, active devices and passive devices.
3. The method of claim 1 , wherein the dielectric material is selected from the group consisting of: silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), fluorinated SiO 2 (FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phospho-silicate glass (BPSG), silsesquioxanes, polymers, carbon (C) doped oxides, phosphorous doped oxides, boron doped oxides and thermosetting polyarylene ethers.
4. The method of claim 1 , wherein the copper has a thickness ranging from approximately 5 nanometers (nm) to approximately 3000 nm.
5. The method of claim 1 , wherein the planarizing is performed by chemical-mechanical-polishing.
6. A method of forming an interconnect structure on a substrate, the substrate including a tungsten contact to one or more electronic devices, the method comprising:
depositing a first dielectric material on the substrate;
depositing a copper diffusion barrier layer on the first dielectric material;
depositing a second dielectric material on the copper diffusion barrier;
forming at least one first opening in the second dielectric material, the first dielectric material and the copper diffusion barrier layer to expose the tungsten contact,
wherein the tungsten contact has a tungsten region including an upper surface;
forming second opening in the second dielectric material over and larger than the at least first opening;
depositing a diffusion barrier liner on the substrate filling the at least one first opening and the second opening, wherein the diffusion barrier liner is selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), ruthenium (Ru), ruthenium nitride (RuN), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), and titanium (Ti);
removing a bottom portion of the diffusion barrier liner to leave side walls of the diffusion barrier liner on the second opening and the at least one opening and exposing the tungsten contact, wherein a portion of the diffusion barrier layer on the side walls of the at least one opening directly contacts the upper surface of the tungsten region;
filling the second opening with copper; and
planarizing a top surface of the interconnect structure.
7. The method of claim 6 , wherein the one or more electronic devices are selected from the group consisting of: capacitors, diodes, resistors, transistors, memory cells, varactors, active devices and passive devices.
8. The method of claim 6 , wherein the dielectric material is selected from the group consisting of: silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), fluorinated SiO 2 (FSG), hydrogenated silicon oxycarbide (SiCOH), porous SiCOH, boro-phospho-silicate glass (BPSG), silsesquioxanes, polymers, carbon (C) doped oxides, phosphorous doped oxides, boron doped oxides and thermosetting polyarylene ethers.
9. The method of claim 6 , wherein the copper has a thickness ranging from approximately 5 nanometers (nm) to approximately 3000 nm.
10. The method of claim 6 , wherein the planarizing is performed by chemical-mechanical-polishing.
11. A method of forming an interconnect structure on a substrate including a tungsten contact to one or more electronic devices, the method comprising:
depositing a dielectric material on the substrate;
forming at least one first opening in the dielectric material to expose the tungsten contact,
wherein the tungsten contact has a tungsten region including an upper surface;
after forming the at least one first opening, depositing a diffusion barrier liner in the at least one first opening including on the exposed tungsten contact;
forming a second opening in the diffusion barrier liner to partially re-expose the tungsten contact, wherein a portion of the single diffusion barrier liner remains in direct contact with the upper surface of the tungsten region,
filling at least the first opening and the second opening with copper; and
planarizing a top surface of the interconnect structure.
12. The method of claim 11 , wherein the diffusion barrier liner is selected from the group consisting of: ruthenium (Ru), ruthenium nitride (RuN), tungsten (W), tungsten nitride (WN), and tungsten silicide (WSi).
13. The method of claim 11 , wherein the diffusion barrier liner is selected from the group consisting of: titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), ruthenium (Ru), ruthenium nitride (RuN), tungsten (W), tungsten nitride (WN), tungsten silicide (WSi), and titanium (Ti).