Granted Patent B2

US 10,373,686 · App. 15/660,552 · Granted Aug 6, 2019

Abstract

Claims (9)

1. A three-dimensional memory system, comprising:

a plurality of pins coupled to a logic circuit, the logic circuit receiving a control signal; and

a memory array comprising a plurality of stacked dies, each die comprising memory cells;

an output stage comprising a sense amplifier, a plurality of buffers for receiving an output of the sense amplifier, and a plurality of pads for receiving an output of the plurality of buffers;

wherein the plurality of pins are configured by the logic circuit to perform a first function when the control signal has a first value and to perform a second function when the control signal has a second value, wherein the first function is providing addresses to the memory array for a read operation resulting in data being read by the sense amplifier, stored in the plurality of buffers, and output from the plurality of buffers onto the plurality of pads, and the second function is providing control signals for testing of the memory system.

2. The system of claim 1 , wherein the control signal is provided by a controller.

3. The system of claim 1 , wherein at least one of the plurality of pins is coupled to the logic circuit through a TSV.

4. The system of claim 1 , wherein at least one of the plurality of pins is a serial pin.

5. The system of claim 1 , wherein at least one of the plurality of pins is a parallel pin.

Assignments (16)