On chip NMOS gapless LDO for high speed microcontrollers
A voltage regulator includes an error amplifier configured to amplify a difference between a feedback voltage and a reference voltage. The regulator also includes an N-type metal-oxide-semiconductor (NMOS) driver circuit. The driver circuit includes an n-type field effect transistor. The driver circuit is communicatively coupled to output of the error amplifier. The regulator further includes a feedback circuit communicatively coupled between the NMOS driver circuit and an input of the error amplifier to provide the feedback voltage.
1. A voltage regulator, comprising:
a first error amplifier configured to amplify a difference between a feedback voltage and a reference voltage;
an N-type metal-oxide-semiconductor (NMOS) driver circuit, including an n-type field effect transistor, communicatively coupled to output of the first error amplifier;
a feedback circuit communicatively coupled between the NMOS driver circuit and an input of the first error amplifier to provide the feedback voltage;
a pump circuit configured to pump current into a gate node of the NMOS driver circuit, wherein an amount of the current is based upon a size of a voltage spike above the reference voltage on an output of the NMOS driver circuit;
a first delay buffer; and
a second delay buffer of a different length than the first delay buffer;
wherein:
a difference between trip voltage of the first delay buffer and the second delay buffer is configured to define a trip voltage for the voltage spike above the reference voltage;
the first delay buffer and the second delay buffer are mutually exclusive;
the first delay buffer and the second delay buffer are both configured to receive input from a same source; and
the second delay buffer is configured to drive a gate of the pump circuit to pump current into the gate node of the NMOS driver circuit.
2. The voltage regulator of claim 1 , further comprising the pump circuit configured to pump current into the gate node of the NMOS driver circuit upon a transient voltage drop at the output of the NMOS driver circuit.
3. The voltage regulator of claim 1 , further comprising a discharge circuit configured to discharge the gate node of the NMOS driver circuit upon a transient voltage overshoot at the output of the NMOS driver circuit.
4. The voltage regulator of claim 1 , further comprising a load connected to output of the NMOS driver circuit, the output of the NMOS driver circuit configured to provide power to the load, the load without a load capacitor connected in parallel between ground and a connection between the output of the NMOS driver circuit and the load.
5. The voltage regulator of claim 1 , further comprising a buffer circuit communicatively coupled to the output of the NMOS driver circuit and configured to signal to a discharge circuit configured to discharge the gate node of the NMOS driver circuit upon a transient voltage overshoot.
6. The voltage regulator of claim 5 , wherein the buffer circuit includes a plurality of inverters with a trip voltage corresponding to the transient voltage overshoot.
7. The voltage regulator of claim 1 , further comprising a buffer circuit communicatively coupled to the output of the NMOS driver circuit and configured to signal to the pump circuit configured to pump current into the gate node of the NMOS driver circuit upon a transient voltage drop.
8. The voltage regulator of claim 7 , wherein the buffer circuit includes a plurality of inverters.
9. The voltage regulator of claim 1 , further comprising the pump circuit configured to pump increased current into the gate node of the NMOS driver circuit based upon an increased load applied to the output of the NMOS driver circuit.
10. The voltage regulator of claim 1 , wherein the first delay buffer and the second delay buffer each include a plurality of elements.
11. The voltage regulator of claim 1 , further comprising a second error amplifier configured to receive output from the NMOS driver circuit, compare the output from the NMOS driver circuit with the reference voltage, and provide output to the first delay buffer and to the second delay buffer.
12. A microcontroller, comprising:
a first error amplifier configured to amplify a difference between a feedback voltage and a reference voltage;
an N-type metal-oxide-semiconductor (NMOS) driver circuit, including an n-type field effect transistor, communicatively coupled to output of the first error amplifier;
a feedback circuit communicatively coupled between the NMOS driver circuit and an input of the first error amplifier to provide the feedback voltage;
a pump circuit configured to pump current into a gate node of the NMOS driver circuit, wherein an amount of the current is based upon a size of a voltage spike above the reference voltage on an output of the NMOS driver circuit;
a first delay buffer; and
a second delay buffer of a different length than the first delay buffer;
wherein:
a difference between trip voltage of the first delay buffer and the second delay buffer is configured to define a trip voltage for the voltage spike above the reference voltage;
the first delay buffer and the second delay buffer both receive input from a same source; and
the second delay buffer is configured to drive a gate of the pump circuit to pump current into the gate node of the NMOS driver circuit.
13. The microcontroller of claim 12 , further comprising the pump circuit configured to pump current into the gate node of the NMOS driver circuit upon a transient voltage drop at the output of the NMOS driver circuit.
14. The microcontroller of claim 12 , further comprising a discharge circuit configured to discharge the gate node of the NMOS driver circuit upon a transient voltage overshoot at the output of the NMOS driver circuit.
15. The microcontroller of claim 12 , further comprising a load connected to output of the NMOS driver circuit, the output of the NMOS driver circuit configured to provide power to the load, the load without a load capacitor connected in parallel between ground and a connection between the output of the NMOS driver circuit and the load.
16. The microcontroller of claim 12 , further comprising a buffer circuit communicatively coupled to the output of the NMOS driver circuit and configured to signal to a discharge circuit configured to discharge the gate node of the NMOS driver circuit upon a transient voltage overshoot.
17. The microcontroller of claim 16 , wherein the buffer circuit includes a plurality of inverters with a trip voltage corresponding to the transient voltage overshoot.
18. The microcontroller of claim 12 , further comprising a buffer circuit communicatively coupled to the output of the NMOS driver circuit and configured to signal to the pump circuit configured to pump current into the gate node of the NMOS driver circuit upon a transient voltage drop.
19. The microcontroller of claim 18 , wherein the buffer circuit includes a plurality of inverters.
20. The microcontroller of claim 12 , further comprising the pump circuit configured to pump increased current into the gate node of the NMOS driver circuit based upon an increased load applied to the output of the NMOS driver circuit.
21. A method, comprising:
through a first error amplifier, amplifying a difference between a feedback voltage and a reference voltage;
communicatively coupling an N-type metal-oxide-semiconductor (NMOS) driver circuit, including an n-type field effect transistor, to output of the first error amplifier;
providing a feedback circuit communicatively coupled between the NMOS driver circuit and an input of the first error amplifier to provide the feedback voltage;
pumping current into a gate node of the NMOS driver circuit, wherein an amount of the current is based upon a size of a voltage spike above the reference voltage on an output of the NMOS driver circuit; and
evaluating a trip voltage defined by a first delay buffer and a second delay buffer of a different length than the first delay buffer, wherein:
a difference between trip voltage of the first delay buffer and the second delay buffer is configured to define the trip voltage for the voltage spike above the reference voltage;
the first delay buffer and the second delay buffer both receive input from a same source; and
the second delay buffer drives a gate of the pump circuit to pump current into the gate node of the NMOS driver circuit.