Safety enhancement for memory controllers
A memory controller includes a generator circuit configured to generate a predetermined pattern of data, an address input, and a memory interface circuit. The memory interface circuit is configured to write the predetermined pattern of data to a memory at an address identified in the address input. The memory interface circuit is further configured to read a stored pattern of data from the memory at the address. The memory controller further includes an integrity checker circuit configured to compare the predetermined pattern of data and the stored pattern of data and identify an error of the memory based upon the comparison.
1. A memory controller, comprising:
a generator circuit configured to generate a predetermined pattern of data;
an address input;
a memory interface circuit configured to:
write the predetermined pattern of data to a memory at an address identified in the address input; and
read a stored pattern of data from the memory at the address; and
an integrity checker circuit configured to:
compare the predetermined pattern of data and the stored pattern of data; and
identify an error of the memory based upon the comparison;
wherein the predetermined pattern of data is configured to cause a maximum number of simultaneous switching outputs of a data bus of the memory given a bit size of the predetermined pattern of data.
2. The memory controller of claim 1 , wherein the predetermined pattern of data includes two portions to be separately written to and read from the memory, and the maximum number of simultaneous switching outputs is a result of respective values from the two portions.
3. The memory controller of claim 1 , wherein the predetermined pattern of data is configured to cause crosstalk in one or more data bits in a data bus of the memory.
4. The memory controller of claim 3 , wherein the predetermined pattern of data includes two portions to be separately written to and read from the memory, and the crosstalk is a result of respective values from the two portions.
5. The memory controller of claim 1 , wherein the memory interface circuit and integrity checker circuit are configured to operate on a period determined by memory refresh command events.
6. The memory controller of claim 1 , wherein the predetermined pattern of data includes an integrity check of one or more address locations in the memory device.
7. The memory controller of claim 1 , wherein the predetermined pattern of data is configured to create a known condition for checking access integrity.
8. The memory controller of claim 1 , wherein the memory interface circuit is configured to:
read and store an existing value from the address before writing the predetermined pattern of data to the address; and
write the existing value to the address after reading the stored pattern of data from the memory at the address.
9. The memory controller of claim 1 , wherein the memory interface circuit is configured to:
receive a memory command for the address before writing the predetermined pattern of data to the address, the predetermined pattern of data not defined by the memory command; and
execute the memory command for the address after reading the stored pattern of data from the memory at the address.
10. A system, comprising:
a processor;
a memory;
a generator circuit configured to generate a predetermined pattern of data;
an address input;
a memory interface circuit configured to:
write the predetermined pattern of data to the memory at an address identified in the address input; and
read a stored pattern of data from the memory at the address; and
an integrity checker circuit configured to:
compare the predetermined pattern of data and the stored pattern of data; and
identify an error of the memory based upon the comparison;
wherein the predetermined pattern of data is configured to cause a maximum number of simultaneous switching outputs of a data bus of the memory given a bit size of the predetermined pattern of data.
11. The system of claim 10 , wherein the predetermined pattern of data includes two portions to be separately written to and read from the memory, and the maximum number of simultaneous switching outputs is a result of respective values from the two portions.
12. The system of claim 10 , wherein the predetermined pattern of data is configured to cause crosstalk in one or more data bits in a data bus of the memory.
13. The system of claim 12 , wherein the predetermined pattern of data includes two portions to be separately written to and read from the memory, and the crosstalk is a result of respective values from the two portions.
14. The system of claim 10 , wherein the memory interface circuit and integrity checker circuit are configured to operate on a period determined by memory refresh command events.
15. The system of claim 10 , wherein the predetermined pattern of data includes an integrity check of one or more address locations in the memory device.
16. The system of claim 10 , wherein the predetermined pattern of data is configured to create a known condition for checking access integrity.
17. The system of claim 10 , wherein the memory interface circuit is configured to:
read and store an existing value from the address before writing the predetermined pattern of data to the address; and
write the existing value to the address after reading the stored pattern of data from the memory at the address.
18. The system of claim 10 , wherein the memory interface circuit is configured to:
receive a memory command for the address before writing the predetermined pattern of data to the address, the predetermined pattern of data not defined by the memory command; and
executing the memory command for the address after reading the stored pattern of data from the memory at the address.