IP Library Granted Patent US 10,713,348
Granted Patent B2
US 10,713,348 · App. 15/904,147 · Granted Jul 14, 2020

System, method, and apparatus for touch panel security

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Quick Facts
Patent No.
US 10,713,348
App. No.
15/904,147
Granted
Jul 14, 2020
Kind
B2
Abstract

Embodiments of the disclosure relate, generally, to touch panel security, and more specifically, to using one or more security features present at one or more electrodes of a sensor module of a touch panel. Embodiments of security features may affect the capacitive coupling at a node of a sensor in a manner detectable by a microcontroller or other logic circuitry, and the location of the security features may provide a basis for an identifier usable to identify a touch panel to a host device with which the touch panel attempts to communicate.

Claims (66)

1. A method of generating an identifier associated with a capacitive sensor, the method comprising:

driving a drive line of a capacitive sensor;

reading reference values received at sense lines of the capacitive sensor responsive to the driven drive line, wherein a first reference value of the reference values is indicative of a first security feature present in the capacitive sensor;

determining location data for a first node associated with the first security feature responsive to the first reference value; and

performing a logical operation on the location data for the first node and a first key to generate a first result.

2. The method of claim 1 , wherein the reference values are indicative of capacitive charge cycles.

3. The method of claim 1 , further comprising retrieving the first key from secure memory.

4. The method claim 1 , further comprising receiving the first key from an external host.

5. The method of claim 1 , further comprising, providing the first result to a communication interface, wherein the communication interface enables communication with an external host.

6. The method of claim 1 , further comprising:

determining location data for a second node associated with a second security feature responsive to a second reference value, wherein a second reference value of the reference values is indicative of a second security feature present in the capacitive sensor;

performing a logical operation on the location data for the second node and a second key to generate a second result; and

combining the first result and the second result to generate a final result.

7. The method of claim 6 , further comprising, providing the final result to a communication interface, wherein the communication interface enables communication with an external host.

8. The method of claim 6 , further comprising retrieving the second key from secure memory.

9. The method of claim 6 , further comprising receiving the second key from an external host.

10. The method of claim 6 , further comprising resolving an identity of a capacitive sensor at least in part responsive to comparing the second result to a pre-calculated result.

11. The method of claim 1 , wherein determining the location data for the first node comprises:

determining an average node reference value;

determining a difference between the first reference value and the average node reference value; and

associating the first reference value with the first security feature responsive to the difference exceeding a threshold.

12. The method of claim 11 , wherein determining the location data for the first node further comprises associating the first reference value with a SPIKE-peak if the first reference value is greater than the average node reference value, and associating the first reference value with a DIP-hole if the first reference value is less than the average node reference value.

13. The method of claim 1 , wherein determining the location data for the first node comprises:

reading reference values into an N×M matrix, wherein N corresponds to a number of drive line associated with the capacitive sensor and M corresponds to a number of sense lines associated with the capacitive sensor;

determining a binomial asymptote trend line responsive to the read reference values of the N×M matrix;

determining a first threshold and a second threshold responsive to the binomial asymptote trend line; and

associating the first reference value with the first security feature responsive to a comparison of the first reference value to the first threshold or second threshold.

14. The method of claim 13 , wherein determining the location data for the first node further comprises associating the first reference value with a SPIKE-peak if the first reference value is greater than the first threshold, and associating the first reference value with a DIP-hole if the first reference value is less than the second threshold.

15. The method of claim 1 , further comprising decreasing a capacitive charge time associated with electrodes of the drive line.

16. A microcontroller, comprising:

a processor; and

a memory, wherein instructions stored on the memory and executable by the processor are configured to enable the microcontroller to:

drive a drive line of a capacitive sensor;

read reference values received at sense lines of the capacitive sensor responsive to the driven drive line, wherein a first reference value of the reference values is indicative of a first security feature present in the capacitive sensor;

determine location data for a first node associated with the first security feature responsive to the first reference value; and

perform a logical operation on the location data for the first node and a first key to generate a first result.

17. The microcontroller of claim 16 , wherein the reference values are indicative of capacitive charge cycles.

18. The microcontroller of claim 16 , wherein the instructions stored on the memory and executable by the processor are configured to enable the microcontroller to retrieve the first key from secure memory.

19. The microcontroller of claim 16 , wherein the instructions stored on the memory and executable by the processor are configured to enable the microcontroller to receive the first key from an external host.

20. The microcontroller of claim 16 , wherein the instructions stored on the memory and executable by the processor are configured to enable the microcontroller to provide the first result to a communication interface, wherein the communication interface enables communication with an external host.

21. The microcontroller of claim 19 , wherein the instructions stored on the memory and executable by the processor are configured to enable the microcontroller to:

determine location data for a second node associated with a second security feature responsive to a second reference value, wherein a second reference value of the reference values is indicative of a second security feature present in the capacitive sensor;

perform a logical operation on the location data for the second node and a second key to generate a second result; and

combine the first result and the second result to generate a final result.

22. The microcontroller of claim 21 , further comprising, providing the final result to a communication interface, wherein the communication interface enables communication with the external host.

23. The microcontroller of claim 21 , further comprising retrieving the second key from secure memory.

24. The microcontroller of claim 21 , further comprising receiving the second key from an external host.

25. The microcontroller of claim 16 , wherein the processor and the memory comprise an integrated circuit package.

26. A method of verifying a touch panel, the method comprising:

retrieving user keys and operand instructions from secure memory of a host device;

providing the user keys and operand instructions with a verification request to a touch panel requesting to provide input data to the host device;

receiving a result data from the touch panel responsive to the verification request, the result data at least partially based on one or more security features present at the touch panel;

comparing the result data to a pre-calculated result byte stored in the secure memory of the host device; and

verifying the result data responsive to the comparison.

27. The method of claim 26 , further comprising, if the result byte is not verified then rejecting the input data from the host device.

28. The method of claim 26 , further comprising, if the result byte is verified then rejecting the input data from the host device.

29. A system, comprising:

a host device; and

a touch panel coupled to the host device and configured to provide input data to the host device, wherein the host device is configured to receive the input data responsive to verifying a verification result received from the touch panel, the touch panel configured to generate the verification result by:

driving a drive line of a capacitive sensor;

reading reference values received at sense lines of the capacitive sensor responsive to the driven drive line, wherein a first reference value of the reference values is indicative of a first security feature present in the capacitive sensor;

determining location data for a first node associated with the first security feature responsive to the first reference value; and

performing a logical operation on the location data for the first node and a first key to generate a first result.

30. The system of claim 29 , wherein the touch panel is configured to provide the verification result to the host device responsive to receiving a verification request from the host device.

31. The system of claim 30 , wherein the verification request comprises user keys and operand instructions.

32. The system of claim 31 , wherein the host device is configured to retrieve the user keys and operand instructions from secure memory of the host and include the user keys and operand instructions in the verification request.

Assignments (15)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2018
From: CHENG, CHI-CHUN; CHIH, HSIN-CHING
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 045034/0933 →