Memory cell with a flat-topped floating gate structure
A memory cell, e.g., a flash memory cell, includes a substrate, a flat-topped floating gate formed over the substrate, and a flat-topped oxide region formed over the flat-topped floating gate. The flat-topped floating gate may have a sidewall with a generally concave shape that defines an acute angle at a top corner of the floating gate, which may improve a program or erase efficiency of the memory cell. The flat-topped floating gate and overlying oxide region may be formed with without a floating gate thermal oxidation that forms a conventional “football oxide.” A word line and a separate erase gate may be formed over the floating gate and oxide region. The erase gate may overlap the floating gate by a substantially greater distance than the word line overlaps the floating gate, which may allow the program and erase coupling to the floating gate to be optimized independently.
1. A flash memory cell, comprising:
a substrate;
a flat-topped floating gate formed over the substrate and having a flat top surface and top corners on opposite sides of the floating gate;
an oxide layer formed over the flat-topped floating gate, the oxide layer including:
(a) a floating gate sidewall portion covering floating gate sidewalls on opposite lateral sides of the floating gate; and
(b) a cap portion located above a top side of the floating gate and including vertically-extending cap portion sidewalls on opposite sides of the cap portion;
wherein the oxide layer defines a stepped transition from the floating gate sidewall portion to the cap portion, the stepped transition covering the top corners of the floating gate, such that the cap portion of the oxide layer has a smaller lateral perimeter footprint than the floating gate sidewall portion of the oxide layer;
a spacer layer formed over the oxide layer, the spacer layer including vertically-extending sidewall regions that are laterally aligned over the top corners of the floating gate;
and a doped source implant region in the substrate adjacent the floating gate, the doped source implant region self-aligned with an edge of the spacer layer.
2. The flash memory cell of claim 1 , wherein the cap portion of the oxide layer is flat-topped.
3. The flash memory cell of claim 1 , further comprising a word line and a separate erase gate formed over the floating gate.
4. The flash memory cell of claim 3 , wherein the word line overlaps the floating gate by a first distance and the erase gate overlaps the floating gate by a second distance substantially larger than the first distance.
5. The flash memory cell of claim 4 , wherein the second distance is at least three times as great as the first distance.
6. The flash memory cell of claim 1 , wherein at least one of the floating gate sidewalls has a generally concave shape.
7. The flash memory cell of claim 6 , wherein the generally concave shape of each floating gate sidewall defines an acute angle at a top corner of the floating gate.
8. The flash memory cell of claim 1 , wherein the oxide layer has a flat bottom surface in contact with the flat top surface of the floating gate, and a flat top surface.
9. The flash memory cell of claim 1 , wherein the flash memory cell is a split-gate cell further comprising:
a further flat-topped floating gate formed over the substrate and having a flat top surface;
a further oxide layer formed over the further flat-topped floating gate;
wherein the doped source region in the substrate extends partially under the floating gate and partially under the further floating gate.
10. The flash memory cell of claim 9 , further comprising:
a word line formed over the floating gate;
a further word line formed over the further floating gate; and
a shared erase gate formed over the floating gate and the further floating gate.
11. The flash memory cell of claim 10 , wherein the word line overlaps the floating gate by a first distance and the erase gate overlaps the floating gate by a second distance substantially larger than the first distance.
12. The flash memory cell of claim 1 , wherein the spacer layer comprises a nitride spacer layer.
13. A flash memory cell, comprising:
a substrate;
a flat-topped floating gate formed over the substrate and having a flat top surface;
an oxide layer formed over the flat-topped floating gate;
a doped source region in the substrate adjacent the floating gate and extending partially under the floating gate; and
a word line extending over a first lateral side of the floating gate and a separate erase gate formed extending over a second lateral side of the floating gate opposite the first lateral side of the floating gate;
wherein the word line overlaps the floating gate in a lateral direction across toward the erase gate by a first distance and the erase gate overlaps the floating gate in an opposing lateral direction toward the word line by a second distance substantially larger than the first distance, wherein the word line and erase gate do not overlap each other.