Flash memory cell and associated decoders
The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
1. A non-volatile memory device comprising:
an array of flash memory cells organized in rows and columns, each flash memory cell comprising a bit line terminal, a word line terminal, an erase gate terminal, a source line terminal, and no other terminals;
a row decoder for receiving row address signals and selecting a row in the array of flash memory cells for a read, program, or erase operation based on the row address signals;
an erase gate decoder for receiving erase gate select signals, selecting one of a plurality of different voltages to generate an erase gate voltage, and applying the erase gate voltage to an erase gate line connected to erase gate terminals of a plurality of flash memory cells in the array;
a source line decoder for receiving source line select signals, selecting one of the plurality of different voltages to generate a source line voltage, and applying the source line voltage to a source line connected to source line terminals of a plurality of flash memory cells in the array;
a voltage shifter for generating one of the plurality of different voltages; and
a column of dummy flash memory cells, wherein each dummy flash memory cell is not used to store data and one or more of the dummy flash memory cells are coupled to a source line during a read or erase operation to pull the source line down to a low voltage or ground, wherein each source line is coupled to the source line terminals of two rows of flash memory cells in the array.
2. The memory device of claim 1 , wherein the row decoder comprises a row decoder circuit for each sector in the array, each sector comprising two row of flash memory cells in the array.
3. The memory device of claim 1 , wherein the erase gate decoder comprises a current limiter for limiting the current generated by the application of the erase gate voltage to the erase gate line.
4. The memory device of claim 1 , wherein the erase gate decoder comprises a deselect circuit for pulling the output of the erase gate decoder to a low voltage in response to the erase gate select signals.
5. The memory device of claim 1 , wherein the erase gate decoder comprises PMOS transistors and no NMOS transistors.
6. The memory device of claim 1 , wherein the source line decoder comprises a monitor circuit for providing a monitor line containing the output of the source line decoder.
7. The memory device of claim 1 , wherein the source line decoder comprises a read deselect circuit for pulling the output of the source line decoder to a low voltage during a read operation.
8. The memory device of claim 1 , wherein the source line decoder comprises a programming deselect circuit for pulling the output of the source line decoder to a low voltage during a programming operation.
9. The memory device of claim 1 , wherein the source line decoder comprises NMOS transistors and no PMOS transistors.
10. The memory device of claim 1 , wherein the source line decoder comprises PMOS transistors and no NMOS transistors.