IP Library Granted Patent US 11,600,523
Granted Patent B2
US 11,600,523 · App. 15/940,807 · Granted Mar 7, 2023

Semiconductor package having exposed redistribution layer features and related methods of packaging and testing

Inventor: ManKit Lam (Colorado Springs, CO)
Assignee: Microchip Technology Incorporated
H01L21/76837G01R31/2813H01L22/14H01L22/32H01L24/02H01L24/03H01L24/05H01L24/08H01L23/3114H01L23/3192H01L24/13H01L2224/024H01L2224/0231H01L2224/0239H01L2224/02331H01L2224/02375H01L2224/02379H01L2224/0345H01L2224/0346H01L2224/0392H01L2224/0401H01L2224/05008H01L2224/05022H01L2224/05024H01L2224/05082H01L2224/05147H01L2224/05166H01L2224/05548H01L2224/05572H01L2224/05613H01L2224/05624H01L2224/05647H01L2224/05655H01L2224/05657H01L2224/05666H01L2224/05671H01L2224/05684H01L2224/131H01L2224/13111H01L2224/13113H01L2224/13118H01L2224/13139H01L2224/13147H01L2224/13157
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Quick Facts
Patent No.
US 11,600,523
App. No.
15/940,807
Granted
Mar 7, 2023
Kind
B2
Abstract

A method of packaging a semiconductor device having a bond pad on a surface thereof includes forming a redistribution material electrically coupled to the bond pad, forming a dielectric material over the redistribution material, and removing a first portion of the dielectric material to expose a first portion of the redistribution material. Semiconductor packages may include a redistribution layer having a first portion adjacent and coupled to a first contact of the package, a second portion exposed by a first opening in a dielectric material, and a redistribution line electrically coupled to a first bond pad, the first portion, and the second portion. Such a package may be tested placing at least one probe needle in contact with at least one terminal of the package, providing a test signal from the probe needle to the package through the terminal, and detecting signals using the needle.

Claims (30)

1. A method of packaging a semiconductor device having at least one testing bond pad and at least one functional bond pad on an active surface of the semiconductor device, wherein the at least one testing bond pad to enable testing the semiconductor device and the at least one functional bond pad to, among other functions, enable reprogramming of circuitry of the semiconductor device, the method comprising:

forming a first redistribution material electrically coupled to the at least one functional bond pad;

forming a second redistribution material electrically coupled to the at least one testing bond pad;

forming a dielectric material on a side of the first and second redistribution materials opposite the respective at least one functional bond pad and the at least one testing bond pad;

removing a first portion of the dielectric material to expose a first portion of the first redistribution material;

removing a second portion of the dielectric material to expose a second portion of the first redistribution material; and

removing a third portion of the dielectric material to expose a first portion of the second redistribution material.

2. The method of claim 1 , further comprising forming an adhesive material on the second portion of the first redistribution material.

3. The method of claim 2 , wherein the adhesive material is a solderable adhesive.

4. The method of claim 3 , further comprising providing a package contact on the adhesive material.

5. The method of claim 4 , wherein the first portion of the first redistribution material is still exposed after providing the package contact.

6. The method of claim 1 , further comprising providing a package contact on the second portion of the first redistribution material.

7. An apparatus, comprising:

electrically and physically accessible terminals of a semiconductor package for a semiconductor device, the terminals including at least one testing terminal and at least one functional terminal, wherein the at least one testing terminal electrically coupled to a testing bond pad of the semiconductor device via a redistribution material and the at least one functional terminal electrically coupled to a functional bond pad of the semiconductor device via a further redistribution material, the testing bond pad and the functional bond pad located on an active surface of the semiconductor device, wherein the at least one testing bond pad to enable testing electrical circuitry of the semiconductor device and the at least one functional bond pad to enable functions including reprogramming electrical circuitry of the semiconductor device; and

at least one contact at a surface of the semiconductor package and electrically coupled to the at least one functional terminal.

8. The apparatus of claim 7 , comprising a dielectric material on, and at least partially covering, the redistribution material, wherein the at least one testing terminal is exposed by an opening defined in the dielectric material.

9. A method, comprising:

providing a semiconductor package for a semiconductor device having at least one testing bond pad and at least one functional bond pad on an active surface of the semiconductor device, the at least one testing bond pad to enable testing electrical circuitry of the semiconductor device and the at least one functional bond pad to enable functions of the electrical circuitry,

placing at least one probe needle in electrical and physical contact with at least one terminal of the semiconductor package, the at least one terminal of the semiconductor package to electrically couple with the at least one testing bond pad of the semiconductor device;

providing one or more test electrical signals from the at least one probe needle to the semiconductor package through the at least one terminal; and

detecting signals indicative of a charge loss or programming margin shift via the at least one terminal of the semiconductor package.

10. The method of claim 9 , further comprising reprogramming electrical circuitry of the semiconductor device responsive to the detected signals.

11. The method of claim 10 , wherein reprogramming electrical circuitry of the semiconductor package device comprises reprogramming electrical circuitry of the semiconductor device via at least one further terminal, the at least one further terminal to electrically couple with the functional bond pad of the semiconductor device.

12. The method of claim 11 , wherein the at least one functional terminal is accessible via a location on the semiconductor package that is remote from a location on the semiconductor package at which the at least one testing terminal is accessible.

13. The method of claim 9 , wherein the semiconductor package is a wafer-level-chip-scale-package.

14. A method, comprising:

providing a semiconductor package for a semiconductor device having at least one testing bond pad and at least one functional bond pad on an active surface of the semiconductor device, the at least one testing bond pad to enable testing electrical circuitry of the semiconductor device and the at least one functional bond pad to enable functions including reprogramming electrical circuitry of the semiconductor device;

providing one or more test signals to a first portion of an exposed first redistribution material electrically coupled to the at least one testing bond pad of the semiconductor device;

detecting signals indicative of a charge loss or programming margin shift; and

reprogramming circuitry of the semiconductor device responsive to the detected signals by providing reprogramming signals to an exposed second redistribution material electrically coupled to the at least one functional bond pad of the semiconductor device.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2018
From: LAM, MANKIT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 045392/0194 →