IP Library Granted Patent US 10,862,294
Granted Patent B2
US 10,862,294 · App. 15/959,870 · Granted Dec 8, 2020

Under-voltage and over-voltage protection using a single comparator

Inventor: Gheorghe Turcan (Bucharest, RO)
Assignee: MICROCHIP TECHNOLOGY INCORPORATED
H02H7/1203H02H3/207H02M1/32H03K5/24H03K7/08
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Quick Facts
Patent No.
US 10,862,294
App. No.
15/959,870
Granted
Dec 8, 2020
Kind
B2
Abstract

An apparatus includes a pulsed-width modulation signal corresponding to a cutoff voltage, a periodic signal generation circuit, a comparator, and logic. The comparator is configured to compare a voltage input with an output of the periodic signal generation circuit and, based on a comparison of the voltage input with the output of the periodic signal generation circuit, generate another pulsed-width modulation signal. The logic is configured to compare the pulsed-width modulation signal and the other pulsed-width modulation signal to determine whether the voltage input has reached the cutoff voltage.

Claims (51)

1. An apparatus, comprising:

a first pulsed-width modulation signal with a duty cycle, the duty cycle corresponding to a first cutoff voltage;

a periodic signal generation circuit;

a comparator configured to:

compare a voltage input with an output of the periodic signal generation circuit; and

based on a comparison of the voltage input with the output of the periodic signal generation circuit, generate a second pulsed-width modulation signal; and

logic configured to compare the first pulsed-width modulation signal and the second pulsed-width modulation signal to determine whether the voltage input has reached the first cutoff voltage.

2. The apparatus of claim 1 , wherein:

the periodic signal generation circuit is configured to generate a sawtooth signal;

an upper bound of the output of the signal generation circuit corresponds to an upper voltage limit for the voltage input; and

a lower bound of the output of the signal generation circuit corresponds to a lower voltage limit for the voltage input.

3. The apparatus of claim 1 , further comprising:

a third pulsed-width modulation signal corresponding to a second cutoff voltage; and

logic configured to compare the second pulsed-width modulation signal and the third pulsed-width modulation signal to determine whether the voltage input has reached the second cutoff voltage.

4. The apparatus of claim 3 , further comprising a single logic output representing whether the voltage input has reached the second cutoff voltage or the first cutoff voltage.

5. The apparatus of claim 1 , wherein the logic configured to compare the first pulsed-width modulation signal and the second pulsed-width modulation signal includes an AND operation with a first input of the first pulsed-width modulation signal and a second input of the second pulsed-width modulation signal.

6. The apparatus of claim 1 , wherein the first pulsed-width modulation signal is delayed to match the output of the comparator.

7. The apparatus of claim 1 , wherein logic configured to compare the first pulsed-width modulation signal and the second pulsed-width modulation signal is configured to provide a logic output to a shut-off of a switched-mode power supply output generator.

8. A method, comprising:

generating a first pulsed-width modulation signal with a duty cycle, the duty cycle corresponding to a first cutoff voltage;

comparing a voltage input with an output of a periodic signal generation circuit;

based on a comparison of the voltage input with the output of the periodic signal generation circuit, generating a second pulsed-width modulation signal; and

comparing the first pulsed-width modulation signal and the second pulsed-width modulation signal to determine whether the voltage input has reached the first cutoff voltage.

9. The method of claim 8 , wherein:

the output of the periodic signal generation circuit is a sawtooth signal;

an upper bound of the output of the signal generation circuit corresponds to an upper voltage limit for the voltage input; and

a lower bound of the output of the signal generation circuit corresponds to a lower voltage limit for the voltage input.

10. The method of claim 8 , further comprising:

generating a third pulsed-width modulation signal corresponding to a second cutoff voltage; and

comparing the second pulsed-width modulation signal and the third pulsed-width modulation signal to determine whether the voltage input has reached the second cutoff voltage.

11. The method of claim 10 , further comprising representing in a single logic output whether the voltage input has reached the second cutoff voltage or the first cutoff voltage.

12. The method of claim 8 , further comprising comparing the first pulsed-width modulation signal and the second pulsed-width modulation signal using an AND operation with a first input of the first pulsed-width modulation signal and a second input of the second pulsed-width modulation signal.

13. The method of claim 8 , further comprising delaying the first pulsed-width modulation signal to match the output of the comparator.

14. The method of claim 8 , wherein comparing the first pulsed-width modulation signal and the second pulsed-width modulation signal includes providing a logic output to a shut-off of a switched-mode power supply output generator.

15. A microcontroller, comprising:

a first pulsed-width modulation generator configured to generate a first pulsed-width modulation signal with a duty cycle, the duty cycle corresponding to a first cutoff voltage;

a periodic signal generation circuit;

a comparator configured to:

compare a voltage input with an output of the periodic signal generation circuit; and

based on a comparison of the voltage input with the output of the periodic signal generation circuit, generate a second pulsed-width modulation signal; and

logic configured to compare the first pulsed-width modulation signal and the second pulsed-width modulation signal to determine whether the voltage input has reached the first cutoff voltage.

16. The microcontroller of claim 15 , wherein:

the periodic signal generation circuit is configured to generate a sawtooth signal;

an upper bound of the output of the signal generation circuit corresponds to an upper voltage limit for the voltage input; and

a lower bound of the output of the signal generation circuit corresponds to a lower voltage limit for the voltage input.

17. The microcontroller of claim 15 , further comprising:

a third pulsed-width modulation generator configured to generate a third pulsed-width modulation signal corresponding to a second cutoff voltage; and

logic configured to compare the second pulsed-width modulation signal and the third pulsed-width modulation signal to determine whether the voltage input has reached the second cutoff voltage.

18. The microcontroller of claim 17 , further comprising a single logic output representing whether the voltage input has reached the second cutoff voltage or the first cutoff voltage.

19. The microcontroller of claim 15 , wherein the logic configured to compare the first pulsed-width modulation signal and the second pulsed-width modulation signal includes an AND operation with a first input of the first pulsed-width modulation signal and a second input of the second pulsed-width modulation signal.

20. The microcontroller of claim 15 , wherein logic configured to compare the first pulsed-width modulation signal and the second pulsed-width modulation signal is configured to provide a logic output to a shut-off of a switched-mode power supply output generator.

Assignments (14)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2018
From: TURCAN, GHEORGHE
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 045612/0504 →