Split-gate flash memory cell with improved read performance
Embodiments of the present disclosure provide systems and methods for improving the read window in a split-gate flash memory cell, e.g., by biasing the control gate terminal with a non-zero (positive or negative) voltage during cell read operations to improve or control the erased state read performance or the programmed state read performance of the cell. A method of operating a split-gate flash memory cell may include performing program operations, performing erase operations, and performing read operations in the cell, wherein each read operation includes applying a first non-zero voltage to the word line, applying a second non-zero voltage to the bit line, and applying a third non-zero voltage V CGR to the control gate.
1. A method of operating a flash memory cell including a floating gate, a source region, a word line, a bit line, and a control gate, the method comprising:
measuring at least one of a programmed (off state) cell current or an erased (on state) cell current of the memory cell; and
selecting a non-zero control gate voltage V CGR based at least on the measured programmed (off state) cell current and/or erased (on state) cell current;
performing program operations in the memory cell;
performing erase operations in the memory cell; and
performing read operations in the memory cell, including applying the non-zero control gate voltage V CGR to the control gate during each read operation wherein applying the selected non-zero control gate voltage V CGR either (a) increases a programmed (off state) read current margin while decreasing an erased (on state) read current margin or (b) increases the erased (on state) read current margin while decreasing the programmed (off state) read current margin, as compared to applying V CGR =0 during each read operation.
2. The method of claim 1 , wherein the flash memory cell comprises a split-gate flash memory cell including a pair of floating gates, a respective word line formed over each respective floating gate, and a single control gate extending over both floating gates.
3. The method of claim 2 , wherein the split-gate flash memory cell comprises a SuperFlash ESF1+ cell.
4. The method of claim 1 , wherein selecting and applying a non-zero control gate voltage V CGR comprises selecting and applying a negative voltage (V CGR <0) to the control gate during each read operation.
5. The method of claim 4 , comprising applying a negative voltage of −1V or less (V CGR ≤0) to the control gate during each read operation.
6. The method of claim 1 , wherein selecting and applying a non-zero control gate voltage V CGR comprises selecting and applying a positive voltage (V CGR >0) to the control gate during each read operation.
7. The method of claim 6 , comprising applying a positive voltage of at least 1V (V CGR ≥0) to the control gate during each read operation.
8. The method of claim 1 , wherein the non-zero voltage V CGR applied to the control gate during each read operation alters a sensed cell current (Ir0 or Ir1), as compared to applying V CGR =0 during each read operation.
9. The method of claim 1 , comprising selecting the non-zero control gate voltage V CGR using a trim bit.
10. The method of claim 1 , wherein measuring at least one of a programmed (off state) cell current or an erased (on state) cell current of the memory cell comprises measuring at least one of an initial programmed (off state) cell current or an initial erased (on state) cell current of the memory cell after fabrication of the memory cell.
11. The method of claim 1 , comprising:
selecting the initial non-zero value of the control gate voltage V CGR ; and
dynamically adjusting the non-zero value of the control gate voltage V CGR over time.
12. The method of claim 1 , wherein performing each read operation includes:
applying a first non-zero voltage to the word line;
applying a second non-zero voltage to the bit line; and
applying the non-zero voltage V CGR to the control gate.
13. The method of claim 12 , wherein the second non-zero voltage to the bit line is the same voltage as the first non-zero voltage applied to the word line.
14. A method of operating a flash memory cell including at least one floating gate, at least one source region, an even word line, an odd word line, and a control gate, the method comprising:
performing program operations in the memory cell;
performing erase operations in the memory cell; and
performing read operations via the even word line, including applying a first control gate voltage V CGR_EVEN to the control gate during each read operation via the even word line; and
performing read operations via the odd word line, including applying a second control gate voltage V CGR_ODD , having a different value than the first control gate voltage V CGR_EVEN , to the control gate during each read operation via the odd word line;
wherein at least one of the first control gate voltage V CGR_EVEN and the second control gate voltage V CGR_ODD is a non-zero voltage.
15. The method of claim 14 , wherein both V CGR_EVEN and V CGR_ODD are non-zero voltages.
16. The method of claim 14 , wherein one of V CGR_EVEN and V CGR_ODD is 0V, such that no voltage is applied to the control gate either during read operations via the even word line or during read operations via the odd word line.
17. A device, comprising:
a plurality of flash memory cells, each including a floating gate, a source region, a word line, a bit line, and a control gate; and
control circuitry configured to:
measure at least one of a programmed (off state) cell current or an erased (on state) cell current of the memory cell; and
select a non-zero control gate voltage V CGR based at least on the measured programmed (off state) cell current and/or erased (on state) cell current;
perform program operations in each flash memory cell;
perform erase operations in each flash memory cell; and
perform read operations in each flash memory cell, wherein the control circuitry is configured to apply the non-zero control gate voltage V CGR to a respective control gate during each read operation, wherein applying the selected non-zero control gate voltage V CGR either (a) increases a programmed (off state) read current margin while decreasing an erased (on state) read current margin or (b) increases the erased (on state) read current margin while decreasing the programmed (off state) read current margin, as compared to applying V CGR =0 during each read operation.
18. The device of claim 17 , comprising control gate voltage V CGR values stored in memory for the plurality of flash memory cells.
19. The device of claim 18 , wherein different control gate voltage V CGR values are stored for different ones of the plurality of flash memory cells.
20. The device of claim 17 , wherein:
each memory cell includes an even word line and an odd word line, and
the control circuitry is configured to:
determine whether each the read operation is associated with the even word line or the odd word line;
for each read operation associated with the even word line, applying a first control gate voltage V CGR_EVEN to the control gate during the respective read operation; and
for each read operation associated with the odd word line, applying a second control gate voltage V CGR_ODD , having a different value than the first control gate voltage V CGR_EVEN , to the control gate during the respective read operation;
wherein at least one of the first control gate voltage V CGR_EVEN and the second control gate voltage V CGR_ODD is a non-zero voltage.