IP Library Granted Patent US 10,700,713
Granted Patent B2
US 10,700,713 · App. 16/044,139 · Granted Jun 30, 2020

System and method for error correction in data communications

Inventors: Peter Graumann (Calgary, CA); Saeed Fouladi Fard (Calgary, CA)
Assignee: MICROSEMI STORAGE SOLUTIONS, INC.
H03M13/2942H03M13/1108H03M13/1148H03M13/255H03M13/2909
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Quick Facts
Patent No.
US 10,700,713
App. No.
16/044,139
Granted
Jun 30, 2020
Kind
B2
Abstract

A method and system are provided for error correction. After row encoding and column encoding, additional codeword data (ACD) and modified parity (P′) may be concurrently created, for each of a plurality of modified column codewords (CCW′), by multiplying initial calculated parity P by a generator matrix G. Each CCW′ may include an ACD portion and a P′ portion such that each bit in the P′ portion of a selected CCW′ is present in the ACD portion for one of the other CCW′. In contrast to known approaches, the method and system may provide modified column codewords such that all data and parity bits are present in two codewords while using only two types of codewords, and without using extra parity-on-parity bits. In a set of modified column codewords, each bit in the modified parity in one modified codeword is present in another codeword.

Claims (49)

1. An encoder comprising:

a processor;

a parity memory in communication with the processor;

a first encoder memory storing a generator matrix; and

a second encoder memory, in communication with the parity memory and the first encoder memory and the processor, the second encoder memory storing statements and instructions for execution by the processor to perform a method of encoding data, the method comprising:

storing, in the parity memory in a first memory state, a plurality R of row codewords comprising R rows of raw data and created row parity, the plurality of row codewords defining initial column codeword data ICD arranged in N columns;

column encoding the initial column data ICD into a plurality N of initial column codewords, and storing, in the parity memory in a second memory state, the plurality N of initial column codewords, each of the plurality N of initial column codewords having a portion of the ICD and having a computed initial parity P;

concurrently creating for each of the N modified column codewords (CCW′), additional column codeword data (ACD) and modified parity (P′) by multiplying the initial parity P by a generator matrix G, each CCW′ including an ACD portion and a P′ portion such that each bit in the P′ portion for a selected CCW′ is present in the ACD portion for one of the other N−1 CCW′;

storing, in the parity memory in a third memory state, the ACD and the P′ for each CCW′;

storing, in the parity memory in a fourth memory state, the modified parity P′ for the N columns; and

transmitting a forward error correction (FEC) block, the FEC block comprising the plurality of row codewords and the modified parity P′ for the N columns stored in the parity memory in the fourth memory state.

2. The encoder of claim 1 wherein the generator matrix defines connection relationships between the initial parity P and the modified parity P′ and the ACD for each of the N columns, the connection relationships causing each bit in P′ for a selected CCW′ to be present in the ACD for one of the other N−1 CCW′.

3. The encoder of claim 1 wherein the generator matrix comprises a plurality of cyclically symmetrical rows such that each row of the generator matrix is a cyclically rotated version of an adjacent row.

4. The encoder of claim 1 wherein an N×N generator matrix is stored in 1/N of the space by storing content of only one row and an indication of how each row is a cyclically rotated version of the stored row.

5. A non-transitory computer-readable memory storing statements and instructions for execution by a processor to perform a method of encoding data, the processor-implemented method comprising:

row encoding R rows of raw data to create row parity for each of the R rows, and storing the row parity in a memory;

creating a plurality R of row codewords comprising the R rows of raw data and the created row parity, the plurality of row codewords defining initial column codeword data (ICD) arranged in N columns;

column encoding the initial column data ICD into a plurality N of initial column codewords, each of the plurality N of initial column codewords having a portion of the ICD and having a computed initial parity P;

concurrently creating, for each of N modified column codewords (CCW′), additional column codeword data (ACD) and modified parity (P′) by multiplying the initial parity P by a generator matrix G, each CCW′ including an ACD portion and a P′ portion such that each bit in the P′ portion of a selected CCW′ is present in the ACD portion for one of the other N−1 CCW′;

storing the modified parity for the N columns in a modified parity memory; and

transmitting a forward error correction (FEC) block, the FEC block comprising the plurality of row codewords and the modified parity for the N columns.

6. The non-transitory computer-readable memory of claim 5 wherein the P′ portions for all N columns together form a set of modified parity bits {P 1 ′, . . . , PN′}, wherein the ACD portions for all N columns together form a set of ACD {ACD 1 , . . . , ACD N }, and wherein all of the modified parity bits {P 1 ′, . . . , PN′} are present in {ACD 1 , . . . , ACD N }.

7. The non-transitory computer-readable memory of claim 6 wherein each of the modified parity bits in the set {P 1 ′, . . . , PN′} is present only once in the set {ACD 1 , . . . , ACD N }.

8. The non-transitory computer-readable memory of claim 5 wherein, in the method, concurrently creating the ACD and the P′ for each of the N CCW′ comprises deriving part of the ACD portion for a selected CCW′ based on contents of the P′ portion from the remaining N−1 CCW′.

9. The non-transitory computer-readable memory of claim 8 wherein, in the method, concurrently creating the ACD and the P′ for each of the N CCW′ comprises deriving the entire ACD portion for a selected CCW based on contents of the P′ from each of the remaining N−1 CCW′.

10. The non-transitory computer-readable memory of claim 5 wherein the generator matrix has a size N×N and wherein the method further comprises:

generating an initial parity matrix having 1 column and N rows and including the computed initial parity P for the plurality N columns;

creating the modified parity P′ by multiplying the initial 1×N parity matrix by the generator matrix of size N×N, the modified parity provided in a modified parity matrix having N columns and 1 row.

11. The non-transitory computer-readable memory of claim 5 wherein the generator matrix defines connection relationships between the initial parity P and the modified parity P′ and the ACD for each of the N columns, the connection relationships causing each bit in P′ for a selected CCW′ to be present in the ACD for one of the other N−1 CCW′.

12. The non-transitory computer-readable memory of claim 5 wherein the generator matrix comprises a plurality of cyclically symmetrical rows such that each row of the generator matrix is a cyclically rotated version of an adjacent row.

13. The non-transitory computer-readable memory of claim 5 wherein an N×N generator matrix is stored in 1/N of the space by storing content of only one row and an indication of how each row is a cyclically rotated version of the stored row.

14. A non-transitory computer-readable memory storing statements and instructions for execution by a processor to perform a method of encoding data, the processor-implemented method comprising:

obtaining initial codeword data ICD;

encoding the ICD into a plurality N of initial codewords (CW), each of the plurality N of initial codewords having a portion of the ICD and having a computed initial parity P;

creating a plurality N of modified codewords (CW′) by multiplying the initial parity P by a generator matrix G to concurrently create, for each of the N modified codewords, additional codeword data (ACD) and modified parity (P′) such that each bit in the P′ for a selected CW′ is present in the ACD for one of the other N−1 CW′;

storing the modified parity for the N modified codewords in a modified parity memory; and

transmitting a forward error correction (FEC) block, the FEC block comprising the ICD and the modified parity for the N modified codewords.

15. The non-transitory computer-readable memory of claim 14 wherein the P′ portions for all N columns together form a set of modified parity bits {P 1 ′, . . . , PN′}, wherein the ICD portions for all N columns together form a set of ICD {ICD 1 , . . . , ICD N }, and wherein all of the modified parity bits {P 1 ′, . . . , PN′}, are present in {ICD 1 , . . . , ICD N }.

16. The non-transitory computer-readable memory of claim 14 wherein each of the modified parity bits in the set {P 1 ′, . . . , PN′}, is present only once in the set {ICD 1 , . . . , ICD N }.

17. The non-transitory computer-readable memory of claim 14 wherein the generator matrix comprises a plurality of cyclically symmetrical rows such that each row of the generator matrix is a cyclically rotated version of an adjacent row.

18. A processor-implemented method of encoding data, comprising:

storing, in a memory in a first memory state, a plurality R of row codewords comprising R rows of raw data and created row parity, the plurality of row codewords defining initial column codeword data ICD arranged in N columns;

column encoding the initial column data ICD into a plurality N of initial column codewords, and storing, in the memory in a second memory state, the plurality N of initial column codewords, each of the plurality N of initial column codewords having a portion of the ICD and having a computed initial parity P;

concurrently creating for each of the N modified column codewords (CCW′), additional column codeword data (ACD) and modified parity (P′) by multiplying the initial parity P by a generator matrix G, each CCW including an ACD portion and a P′ portion such that each bit in the P′ portion for a selected CCW′ is present in the ACD portion for one of the other N−1 CCW′;

storing, in the parity memory in a third memory state, the ACD and the P′ for each CCW′;

storing, in the parity memory in a fourth memory state, the modified parity P′ for the N columns; and

transmitting a forward error correction (FEC) block, the FEC block comprising the plurality of row codewords and the modified parity P′ for the N columns stored in the parity memory in the fourth memory state.

19. The processor-implemented method of claim 18 wherein the P′ portions for all N columns together form a set of modified parity bits {P 1 ′, . . . , PN′}, wherein the ACD portions for all N columns together form a set of ACD {ACD 1 , . . . , ACD N }, and wherein all of the modified parity bits {P 1 ′, . . . , PN′} are present in {ACD 1 , . . . , ACD N }.

20. The processor-implemented method of claim 18 wherein the generator matrix comprises a plurality of cyclically symmetrical rows such that each row of the generator matrix is a cyclically rotated version of an adjacent row.

Assignments (12)
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2018
From: GRAUMANN, PETER; FARD, SAEED FOULADI
To: MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 046474/0369 →