Digital control of switched boundary mode interleaved power converter with reduced crossover distortion
A circuit arrangement, signal processor, and method for interleaved switched boundary mode power conversion are disclosed. The circuit arrangement comprises at least an input for receiving an alternating input voltage from a power supply; an output to provide an output voltage to a load; a first interleaved circuit comprising: a first energy storage device; and a first controllable switching device; and one or more secondary interleaved circuits, each comprising: a secondary energy storage device; and a secondary controllable switching device; and a signal processor. The signal processor is connected to the controllable switching devices and comprises at least a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the one or more secondary controllable switching devices The signal processor is configured to disable one or more of the interleaved circuits when the alternating input voltage is lower than a first threshold voltage to reduce the zero-crossing time.
1. A circuit arrangement for interleaved switched boundary mode power conversion, comprising at least:
an input for receiving an alternating input voltage from a power supply;
an output to provide an output voltage to a load;
a first interleaved circuit comprising:
a first energy storage device; and
a first controllable switching device; and
one or more secondary interleaved circuits, each comprising:
a secondary energy storage device; and
a secondary controllable switching device;
said circuit arrangement further comprising a signal processor, connected to the controllable switching devices; the signal processor comprising at least
a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and
one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the one or more secondary controllable switching devices, wherein
the signal processor is configured to disable one or more of the interleaved circuits when the alternating input voltage is lower than a first threshold voltage to reduce a zero-crossing time, and wherein
the signal processor is further configured to control a gain multiplier for at least one of an on-time period of the controllable switching devices and a switching cycle time, wherein in case one or more of the interleaved circuits are disabled, the gain multiplier is increased.
2. The circuit arrangement of claim 1 , wherein the signal processor is further configured to re-enable one or more of the interleaved circuits when the alternating input voltage is higher than the first threshold voltage.
3. The circuit arrangement of claim 1 , wherein the increase of the gain multiplier depends on the number of disabled interleaved circuits.
4. The circuit arrangement of claim 1 , wherein the increase of the gain multiplier corresponds to the quotient of the total number of interleaved circuits in the circuit arrangement by the number of non-disabled interleaved circuits.
5. The circuit arrangement of claim 1 , wherein the signal processor is further configured to control the gain multiplier so that the open loop system bandwidth is constant.
6. The circuit arrangement of claim 1 , wherein the signal processor is further configured to control, in a given switching cycle, an on-time period of each non-disabled controllable switching device to correspond to each other.
7. The circuit arrangement of claim 1 , wherein the signal processor is further configured to control phases between the on-time periods of the non-disabled switching devices, so that the on-time periods are distributed over the given switching cycle to reduce an overall current ripple at the input.
8. The circuit arrangement of claim 1 , wherein the signal processor is configured to disable an increasing number of the controllable switching devices with a decrease of the alternating input voltage.
9. The circuit arrangement of claim 1 , wherein the signal processor is configured to vary which interleaved circuits are disabled within a half-cycle of the alternating input voltage to equalize stress of the interleaved circuits.
10. The circuit arrangement of claim 1 , wherein the signal processor is configured to vary which interleaved circuits are disabled in two subsequent half-cycles of the alternating input voltage to equalize stress of the interleaved circuits.
11. The circuit arrangement of claim 1 , wherein the signal processor is configured with multiple different threshold voltages, wherein the first threshold voltage is the highest of the threshold voltages and each other threshold voltage of the multiple threshold voltages is half of a another threshold voltage of the multiple threshold voltages; and wherein the signal processor is configured to disable a number of interleaved circuits when the alternating input voltage falls below one of the multiple threshold voltages.
12. The circuit arrangement of claim 11 , wherein the number of threshold voltages depends on the number of interleaved circuits of the circuit arrangement.
13. The circuit arrangement of claim 11 , wherein the number of threshold voltages corresponds to the binary logarithm of the number of interleaved circuits of the circuit arrangement.
14. The circuit arrangement of claim 1 , wherein the number of interleaved circuits of the circuit arrangement is a power of 2.
15. The circuit arrangement of claim 11 , wherein one or more of the threshold voltages are predefined.
16. The circuit arrangement of claim 11 , wherein the number of threshold voltages is dynamically determined, based on a peak level of the input voltage.
17. The circuit arrangement of claim 1 , wherein the signal processor during zero-current switching is configured to control the switching devices at least at one zero-current point of the associated energy storage device.
18. The circuit arrangement of claim 1 , wherein the signal processor is configured to control the switching devices from an off-state to an on-state at the at least one zero-current point.
19. The circuit arrangement of claim 1 , wherein the signal processor is configured to control the on-time periods to correspond to each other in every switching cycle.
20. The circuit arrangement of claim 1 , wherein the signal processor is configured to control the phases between the on-time periods of the first and the one or more secondary switching controllers in every switching cycle.
21. The circuit arrangement of claim 1 , wherein each switching cycle controller is configured for PWM operation of the associated controllable switching device.
22. The circuit arrangement of claim 1 , wherein the signal processor comprises a delay module, configured so that the at least one switching point is delayed for a predetermined delay time.
23. The circuit arrangement of claim 1 , wherein the signal processor further comprises a limiter, configured to provide maximum on-time information to the PWM module.
24. The circuit arrangement of claim 1 , wherein the circuit arrangement is a boost converter.
25. The circuit arrangement of claim 1 , further comprising a rectifier circuit to rectify an AC input voltage.
26. A signal processor for use in a circuit arrangement for interleaved switched boundary mode power conversion with at least a first controllable switching device and one or more secondary controllable switching devices; said signal processor being connectable to the controllable switching devices and being configured for zero-current switching of the switching devices; wherein the signal processor comprises at least:
a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and
one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the one or more secondary controllable switching devices, wherein
the signal processor is configured to disable one or more of the controllable switching devices when an alternating input voltage of the circuit arrangement is lower than a first threshold voltage, and wherein
the signal processor is further configured to control a gain multiplier for at least one of an on-time period and a switching cycle time of at least one of the controllable switching devices, wherein in case one or more of the controllable switching devices are disabled, the gain multiplier is increased.
27. A method of interleaved switched boundary mode power conversion with a circuit comprising an input for receiving an alternating input voltage from a power supply; an output to provide an output voltage to a load; a first controllable switching device; and one or more secondary controllable switching devices; wherein
one or more of the controllable switching devices are disabled when the alternating input voltage is lower than a first predefined voltage, and wherein
a gain multiplier for at least one of an on-time period and a switching cycle time of at least one of the controllable switching devices is controlled, wherein in case one or more of the controllable switching devices are disabled, the gain multiplier is increased.
28. A non-transitory machine-readable medium including contents that are configured to cause a signal processor to conduct the method of claim 27 .
29. A circuit arrangement for interleaved switched boundary mode power conversion, comprising at least:
an input for receiving an alternating input voltage from a power supply;
an output to provide an output voltage to a load;
a first interleaved circuit comprising:
a first energy storage device; and
a first controllable switching device; and
one or more secondary interleaved circuits, each comprising:
a secondary energy storage device; and
a secondary controllable switching device;
said circuit arrangement further comprising a signal processor, connected to the controllable switching devices; the signal processor comprising at least
a first switching cycle controller, configured for cycled zero-current switching operation of the first controllable switching device; and
one or more secondary switching cycle controllers, configured for cycled zero-current switching operation of the one or more secondary controllable switching devices, wherein
the signal processor is configured to disable one or more of the interleaved circuits when the alternating input voltage is lower than a first threshold voltage, and wherein
the signal processor is further configured in case one or more of the interleaved circuits are disabled, to increase at least one of an on-time period and a switching cycle time of one or more of the controllable switching devices of one or more of the interleaved circuits that are not disabled.