Granted Patent B2

US 10,872,043 · App. 16/052,361 · Granted Dec 22, 2020

Inventors: Laurent Le Goffic (Nantes, FR); Sylvain Garnier (Nantes, FR)

Assignee: MICROCHIP TECHNOLOGY INCORPORATED

G06F12/1425G06F21/64G06F21/79G06F2212/1052G06F2221/033G06F2221/2113

Abstract

Claims (51)

1. A microcontroller configured to provide secure integrity checking of code or data stored in the microcontroller, the microcontroller comprising:

a processor;

one or more memory devices collectively defining a memory space of the microcontroller, the memory space including a plurality of memory regions;

a security attribution unit storing security attributes of each of the plurality of memory regions, the security attributes defining at least one secure memory region and at least one non-secure memory region;

a plurality of integrity check tables, each integrity check table stored in one of the plurality of memory regions and including information indicating a storage location of a respective piece of code within the memory space of the microcontroller, wherein the integrity check table corresponding to a respective piece of code includes a header, information indicating a memory address of the respective piece of code, information indicating a size of the respective piece of code, and information indicating an expected result of an integrity check of the respective piece of code;

an integrity checking unit having access to the plurality of memory regions and configured to:

receive an integrity check request for checking the integrity of a first piece of code stored in the memory space of the microcontroller;

based on the received integrity check request, access a first integrity check table of the plurality of integrity check tables, the first integrity check table indicating a storage location of the first piece of code;

determine whether the first integrity check table and the first piece of code are stored in the same memory region of the plurality of memory regions;

determine whether to perform the requested integrity check based at least on the determination of whether the first integrity check table and the first piece of code are stored in the same memory region; and

if it is determined to perform the requested integrity check, access and perform an integrity check of the first piece of code.

2. The microcontroller of claim 1 , wherein the integrity checking unit has full access to all of the plurality of memory regions of the microcontroller.

3. The microcontroller of claim 1 , wherein the integrity checking unit is further configured to:

determine, based on the first integrity check table, a particular memory region in which the first piece of code is stored;

access, from the security attribution unit, security attributes of the particular memory region; and

determine whether to perform the requested integrity check based at least on (a) the determination of whether the first integrity check table and the first piece of code are stored in the same memory region and (b) the security attributes of the particular memory region.

4. The microcontroller of claim 1 , wherein the integrity checking unit is embodied as a hardware device provided in addition to the one or more memory devices.

5. The microcontroller of claim 1 , wherein the integrity checking unit is embodied by the processor executing code stored in a secure read-only memory (ROM) of the microcontroller.

6. The microcontroller of claim 1 , wherein the integrity checking unit is further configured to, if it is determined not to perform the requested integrity check, communicate an error notification to a requestor of the integrity check request indicating a reason for denial of the requested integrity check.

7. The microcontroller of claim 1 , wherein the information indicating an expected result of an integrity check of the respective piece of code comprises a value of a hash or cyclic redundancy check (CRC).

8. The microcontroller of claim 1 , wherein the security attributes of at least one of the plurality of memory regions are configurable or adjustable by a code provider that loads at least one piece of code in at least one memory device of the microcontroller.

9. A microcontroller configured to provide secure integrity checking of code or data stored in the microcontroller, the microcontroller comprising:

a processor;

one or more memory devices collectively defining a memory space of the microcontroller, the memory space including a plurality of memory regions, wherein boundaries of at least one of the plurality of memory regions are configurable or adjustable by a code provider that loads at least one piece of code in at least one memory device of the microcontroller;

a security attribution unit storing security attributes of each of the plurality of memory regions, the security attributes defining at least one secure memory region and at least one non-secure memory region;

a plurality of integrity check tables, each integrity check table stored in one of the plurality of memory regions and including information indicating a storage location of a respective piece of code within the memory space of the microcontroller;

an integrity checking unit having access to the plurality of memory regions and configured to:

receive an integrity check request for checking the integrity of a first piece of code stored in the memory space of the microcontroller;

based on the received integrity check request, access a first integrity check table of the plurality of integrity check tables, the first integrity check table indicating a storage location of the first piece of code;

determine whether the first integrity check table and the first piece of code are stored in the same memory region of the plurality of memory regions;

determine whether to perform the requested integrity check based at least on the determination of whether the first integrity check table and the first piece of code are stored in the same memory region; and

if it is determined to perform the requested integrity check, access and perform an integrity check of the first piece of code.

10. A method for providing secure integrity checking of code stored in a microcontroller including a processor and one or more memory devices collectively defining a memory space of the microcontroller, the memory space including a plurality of memory regions, the method comprising:

storing, in a security attribution unit of the microcontroller, security attributes of each of the plurality of memory regions, the security attributes defining at least one secure memory region and at least one non-secure memory region;

storing a plurality of integrity check tables in the memory space of the microcontroller, wherein each integrity check table is stored in one of the plurality of memory regions and includes information indicating a storage location of a respective piece of code within the memory space of the microcontroller;

performing, by an integrity checking unit of the microcontroller, an integrity check management process including:

receiving an integrity check request for checking the integrity of a first piece of code stored in the memory space of the microcontroller;

based on the received integrity check request, accessing a first integrity check table of the plurality of integrity check tables, the first integrity check table indicating a first memory region in which the first piece of code is located and security attributes of the first memory region;

determining whether the first integrity check table and the first piece of code are stored in the same memory region of the plurality of memory regions;

determining whether to perform the requested integrity check based at least on (a) the determination of whether the first integrity check table and the first piece of code are stored in the same memory region and (b) the security attributes of the first memory region indicated in the first integrity check table, including:

determining to perform the requested integrity check if at least one of (a) the first integrity check table and the first piece of code are stored in the same memory region or (b) the security attributes indicate the first memory region is non-secure; and

determining not to perform the requested integrity check if both (a) the first integrity check table and the first piece of code are not stored in the same memory region and (b) the security attributes indicate the first memory region is secure; and

if it is determined to perform the requested integrity check, accessing and performing an integrity check of the first piece of code.

11. The method of claim 10 , wherein the integrity checking unit has full access to all of the plurality of memory regions of the microcontroller.

12. The method of claim 10 , wherein the integrity checking unit configured to perform the integrity check management process comprises a hardware unit provided in addition to the one or more memory devices.

13. The method of claim 10 , wherein performing the integrity check management process by the integrity checking unit comprises the processor of the microcontroller executing code stored in a secure read-only memory (ROM) of the microcontroller.

14. The method of claim 10 , wherein performing, by the integrity checking unit of the microcontroller, the integrity check management process includes determining not to perform the requested integrity check, and in response, communicating an error notification to a requestor of the integrity check request indicating a reason for denial of the requested integrity check.

15. The method of claim 10 , wherein the integrity check table corresponding to each respective piece of code includes a header, information indicating a memory address of the respective piece of code, information indicating a size of the respective piece of code, and information indicating an expected result of an integrity check of the respective piece of code.

16. The method of claim 10 , wherein the information indicating an expected result of an integrity check of the respective piece of code comprises a value of a hash or cyclic redundancy check (CRC).

17. The method of claim 10 , further comprising configuring or adjusting security attributes of at least one of the plurality of memory regions based on input from a code provider that loads at least one piece of code in at least one memory device of the microcontroller.

18. The method of claim 10 , further comprising configuring or adjusting boundaries of at least one of the plurality of memory regions based on input from a code provider that loads at least one piece of code in at least one memory device of the microcontroller.

Assignments (16)

Continuity (2)

Cited By (1)

US 12,705,186