Method of making embedded memory device with silicon-on-insulator substrate
View Patent ↗A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.
1. A method of forming a semiconductor device, comprising:
providing a substrate that includes bulk silicon, a first insulation layer directly over the bulk silicon, and a silicon layer directly over the first insulation layer;
removing the silicon layer and the first insulation layer from a first area of the substrate, while maintaining the first insulation layer and the silicon layer in a second area of the substrate;
forming a first polysilicon layer disposed over and insulated from the bulk silicon in the first area of the substrate and over and insulated from the silicon layer in the second area of the substrate;
forming a second polysilicon layer disposed over and insulated from the first polysilicon layer in the first and second areas of the substrate;
performing one or more etches to selectively remove portions of the first and second polysilicon layers in the first area of the substrate while maintaining the first and second polysilicon layers in the second area of the substrate, wherein the one or more etches result in pairs of spaced apart stack structures of the first and second polysilicon layers in the first area of the substrate;
forming first source regions in the bulk silicon in the first area of the substrate each disposed between one of the pairs of stack structures;
forming a third polysilicon layer disposed over and insulated from the bulk silicon in the first area of the substrate and disposed between the stack structures;
forming one or more protective layers in the first area of the substrate over the stack structures and the third polysilicon layer;
after the forming of the one or more protective layers in the first area of the substrate, removing the first and second polysilicon layers from the second area of the substrate;
after the removing of the first and second polysilicon layers from the second area of the substrate, forming logic devices in the second area of the substrate, wherein the forming of each of the logic devices includes:
forming spaced apart second source and first drain regions in the silicon layer, and
forming a conductive gate over and insulated from a portion of the silicon layer between the second source and first drain regions;
after the forming of the logic devices, removing the one or more protective layers in the first area of the substrate;
etching portions of the third polysilicon layer in the first area of the substrate to form a plurality of blocks of the third polysilicon layer each disposed adjacent to one of the stack structures; and
forming second drain regions in the bulk silicon in the first area of the substrate, wherein each second drain region is disposed adjacent to one of the blocks of the third polysilicon layer.
2. The method of claim 1 , wherein the first source and second drain regions extend deeper into the bulk silicon than do the second source and first drain regions into the silicon layer.
3. The method of claim 1 , wherein the first source and second drain regions extend deeper into the bulk silicon than a thickness of the silicon layer.
4. The method of claim 1 , wherein the conductive gates include a metal material.
5. The method of claim 4 , wherein the conductive gates are insulated from the silicon layer by a high K insulation material.