Methods of reinforcing integrated circuitry of semiconductor devices and related semiconductor devices and packages
View Patent ↗Methods of making a semiconductor device packages may involve placing a metal material at least partially around a region of integrated circuitry embedded within an active surface of a semiconductor die, the metal material located on the active surface. At least a portion of the metal material may be left electrically disconnected from the region of integrated circuitry. The semiconductor die and the metal material may be encapsulated in an encapsulant material, the encapsulant material extending to a height above the active surface higher than a maximum height of the metal material above the active surface.
1. A method of making a semiconductor device package, comprising:
placing a metal material entirely around each region of a plurality of regions of integrated circuitry on an active surface of a semiconductor die;
leaving at least a portion of the metal material electrically disconnected from each region of integrated circuitry; and
encapsulating the semiconductor die and the metal material in an encapsulant material, the encapsulant material extending to a height above the active surface higher than a maximum height of the metal material above the active surface.
2. The method of claim 1 , wherein placing the metal material entirely around each region of the plurality of regions of integrated circuitry, comprises: building up the metal material to the maximum height, the maximum height being greater than or equal to a second-greatest maximum height of any other structure located above the active surface, and encapsulated within the encapsulant material.
3. The method of claim 2 , wherein building up the metal material comprises sequentially placing a masking material above the active surface, patterning the masking material to form trenches or holes, and placing portions of the metal material in the trenches or holes.
4. The method of claim 1 , further comprising electrically connecting at least another portion of the metal material to at least one region of the plurality of regions of integrated circuitry, the at least another portion of the metal material being electrically disconnected from the at least a portion of the metal material.
5. The method of claim 1 , further comprising forming the integrated circuitry of the plurality of regions to comprise at least a portion of a relaxation oscillator.
6. The method of claim 1 , wherein forming the integrated circuitry of the plurality of regions comprises forming a resistor or a capacitor in at least one region of the plurality of regions.
7. The method of claim 1 , wherein placing the metal material entirely around each region of the plurality of regions of integrated circuitry on the active surface of the semiconductor die comprises forming one of a wall, a fence, or a cage of the metal material entirely around each region.
8. A semiconductor device, comprising:
a semiconductor die comprising an active surface;
a plurality of regions of integrated circuitry on the active surface; and
a metal material entirely laterally surrounding each region of the plurality of regions of integrated circuitry on the active surface, at least a portion of the metal material electrically disconnected from each region of integrated circuitry.
9. The semiconductor device of claim 8 , wherein the plurality of regions of integrated circuitry comprises at least a portion of a relaxation oscillator.
10. The semiconductor device of claim 9 , wherein at least one region of the plurality of regions of integrated circuitry comprises a resistor or a capacitor.
11. The semiconductor device of claim 9 , wherein the metal material is configured to mechanically reinforce the region of integrated circuitry to cause an actual frequency of the relaxation oscillator to remain within about 0.25% of a target frequency when the semiconductor device is exposed to environmental temperatures ranging from about −40° C. to about 94° C.
12. The semiconductor device of claim 8 , wherein the metal material forms a grid when viewed perpendicular to the active surface.
13. The semiconductor device of claim 8 , wherein at least another portion of the metal material is electrically connected to at least one region of the plurality of regions of integrated circuitry, the at least another portion of the metal material being electrically disconnected from the at least a portion of the metal material.
14. The semiconductor device of claim 8 , wherein the metal material entirely surrounding each region of the plurality of regions of integrated circuitry comprises one of a wall, a fence, or a cage of the metal material extending entirely around each region.
15. A semiconductor device package, comprising:
the semiconductor device of claim 8 ; and
an encapsulant material extending over the active surface and encapsulating at least the active surface of the semiconductor die and the metal material, the encapsulant material extending to a height above the active surface higher than a maximum height of the metal material above the active surface.
16. The semiconductor device package of claim 15 , wherein the plurality of regions of integrated circuitry comprises at least a portion of a relaxation oscillator.
17. The semiconductor device package of claim 16 , wherein the portion of the relaxation oscillator comprises a resistor or a capacitor.
18. The semiconductor device package of claim 16 , wherein the metal material is configured to mechanically reinforce the at least one region of integrated circuitry responsive at least to temperature change-induced stress, to maintain an actual frequency of the relaxation oscillator after packaging within about 0.25% of a target frequency when the semiconductor device is exposed to environmental temperatures ranging from about −40° C. to about 94° C.
19. The semiconductor device package of claim 16 , wherein the maximum height is greater than or equal to a second-greatest maximum height of any other structure located above the active surface and encapsulated within the encapsulant material.
20. The semiconductor device package of claim 16 , wherein at least one region comprises a plurality of regions and the metal material at least partially surrounds each of the plurality of regions of integrated circuitry on the active surface, the metal material forming a grid when viewed perpendicular to the active surface.
21. The semiconductor device package of claim 16 , wherein the metal material at least partially surrounding the at least one region of integrated circuitry comprises one of a wall, a fence or a cage of the metal material extending at least partially around the at least one region.
22. A clock module, comprising:
a semiconductor device of claim 8 ,
wherein one or more regions of the plurality of regions of integrated circuitry is operatively configured as a relaxation oscillator configured to provide synchronization timing for the clock module; and
an encapsulant material extending over the active surface and encapsulating at least an active surface portion of the semiconductor die and the metal material, the encapsulant material extending to a height above the active surface higher than a maximum height of the metal material above the active surface.
23. A microcontroller unit, comprising:
a semiconductor device of claim 8 ,
wherein one or more regions of the plurality of regions of the integrated circuitry is operatively configured as a relaxation oscillator configured to provide synchronization timing for the microcontroller unit, and
an encapsulant material extending over the active surface and encapsulating at least an active surface portion of the semiconductor die and the metal material, the encapsulant material extending to a height above the active surface higher than a maximum height of the metal material above the active surface.