Non-volatile split gate memory cells with integrated high K metal control gates and method of making same
View Patent ↗A memory device includes a memory cell, a logic device and a high voltage device formed on the same semiconductor substrate. Portions of the upper surface of the substrate under the memory cell and the high voltage device are recessed relative to the upper surface portion of the substrate under the logic device. The memory cell includes a polysilicon floating gate disposed over a first portion of a channel region of the substrate, a polysilicon word line gate disposed over a second portion of the channel region, a polysilicon erase gate disposed over a source region of the substrate, and a metal control gate disposed over the floating gate and insulated from the floating gate by a composite insulation layer that includes a high-K dielectric. The logic device includes a metal gate disposed over the substrate. The high voltage device includes a polysilicon gate disposed over the substrate.
1. A method of making a memory device on a semiconductor substrate having an upper surface and first, second and third areas, comprising:
recessing portions of the upper surface in the first and third areas relative to a portion of the upper surface in the second area;
forming a memory cell by:
forming a first source region and a first drain region in the substrate under the recessed portion of the upper surface in the first area of the substrate, with a first channel region of the substrate extending between the first source region and the first drain region,
forming a polysilicon floating gate disposed vertically over and insulated from a first portion of the first channel region,
forming a poly silicon word line gate disposed vertically over and insulated from a second portion of the first channel region,
forming a polysilicon erase gate disposed vertically over and insulated from the first source region, and
forming a metal control gate disposed vertically over and insulated from the floating gate;
forming a logic device by:
forming a second source region and a second drain region in the second area of the substrate, with a second channel region of the substrate extending between the second source region and the second drain region, and
forming a metal gate disposed vertically over and insulated from the second channel region;
forming a high voltage device by:
forming a third source region and a third drain region in the substrate under the recessed portion of the upper surface in the third area of the substrate, with a third channel region of the substrate extending between the third source region and the third drain region, and
forming a poly silicon gate disposed vertically over and insulated from the third channel region.
2. The method of claim 1 , wherein the metal control gate is formed of Ti and TiN.
3. The method of claim 2 , wherein the metal control gate is insulated from the floating gate by at least a layer of high K dielectric material.
4. The method of claim 2 , wherein the metal control gate is insulated from the floating gate by a layer of high K dielectric material disposed between a pair of oxide layers.
5. The method of claim 1 , wherein the metal gate is insulated from the second channel region by at least a layer of high K dielectric material.
6. The method of claim 5 , wherein the metal gate is formed of TiN.
7. The method of claim 1 , wherein the forming of the polysilicon word line gate, the polysilicon erase gate and the polysilicon gate comprises:
forming a layer of polysilicon over and insulated from the substrate; and
selectively removing portions of the polysilicon layer in the first area leaving behind the polysilicon word line gate and the polysilicon erase gate, and in the third area leaving behind the polysilicon gate.
8. The method of claim 1 , further comprising:
forming SiGe on the upper surface of the substrate over the first, second and third drain regions and over the second and third source regions.
9. The method of claim 1 , wherein the recessing of the portions of the upper surface in the first and third areas comprises:
forming an insulation layer over the upper surface in the first, second and third areas;
removing the insulation layer from the first and third areas but not from the second area;
oxidizing the upper surface in the first and third areas but not in the second area.
10. The method of claim 1 , wherein:
the word line gate is insulated from the substrate by a first insulation having a first thickness;
the floating gate is insulated from the substrate by a second insulation having a second thickness;
the polysilicon gate is insulated from the substrate by a third insulation having a third thickness; and
the first thickness is less than the second thickness, and the second thickness is less than the third thickness.
11. The method of claim 1 , wherein the forming of the first, second and third drain regions, and the second and third source regions, comprise:
performing an implantation that simultaneously forms the first drain region in the first area, the second source and the second drain regions in the second area, and the third source and the third drain regions in the third area.
12. The method of claim 1 , wherein a top surface of the control gate, a top surface of the metal gate and a top surface of the polysilicon gate are co-planar.
13. A memory device, comprising:
a semiconductor substrate having an upper surface and first, second and third areas, wherein portions of the upper surface in the first and third areas are recessed relative to a portion of the upper surface in the second area;
a memory cell that includes:
a first source region and a first drain region formed in the substrate under the recessed portion of the upper surface in the first area of the substrate, with a first channel region of the substrate extending between the first source region and the first drain region,
a polysilicon floating gate disposed vertically over and insulated from a first portion of the first channel region,
a polysilicon word line gate disposed vertically over and insulated from a second portion of the first channel region,
a polysilicon erase gate disposed vertically over and insulated from the first source region, and
a metal control gate disposed vertically over and insulated from the floating gate;
a logic device that includes:
a second source region and a second drain region formed in the second area of the substrate, with a second channel region of the substrate extending between the second source region and the second drain region, and
a metal gate disposed vertically over and insulated from the second channel region;
a high voltage device that includes:
a third source region and a third drain region formed in the substrate under the recessed portion of the upper surface in the third area of the substrate, with a third channel region of the substrate extending between the third source region and the third drain region, and
a polysilicon gate disposed vertically over and insulated from the third channel region.
14. The device of claim 13 , wherein the metal control gate is formed of Ti and TiN.
15. The device of claim 14 , wherein the metal control gate is insulated from the floating gate by at least a layer of high K dielectric material.
16. The device of claim 14 , wherein the metal control gate is insulated from the floating gate by a layer of high K dielectric material disposed between a pair of oxide layers.
17. The device of claim 13 , wherein the metal gate is insulated from the second channel region by at least a layer of high K dielectric material.
18. The device of claim 17 , wherein the metal gate is formed of TiN.
19. The device of claim 13 , further comprising:
SiGe disposed directly on the upper surface of the substrate over the first, second and third drain regions and over the second and third source regions.
20. The device of claim 13 , wherein:
the word line gate is insulated from the substrate by a first insulation having a first thickness;
the floating gate is insulated from the substrate by a second insulation having a second thickness;
the polysilicon gate is insulated from the substrate by a third insulation having a third thickness;
the first thickness is less than the second thickness, and the second thickness is less than the third thickness.
21. The device of claim 13 , wherein a top surface of the control gate, a top surface of the metal gate and a top surface of the polysilicon gate are co-planar.