Shaping traffic on PLCA-enabled 10SPE networks
A 10SPE network node includes a processor, a memory, instructions in the memory configured to cause the processor to generate data to be sent to other nodes, and a network stack. The network stack includes circuitry configured to delay transmission of data in a sending slot in a transmission cycle on a 10SPE network based upon a bandwidth sharing scheme.
1. A 10SPE network node, comprising:
a processor;
a memory;
instructions in the memory configured to cause the processor to generate data to be sent to other nodes; and
a network stack including circuitry configured to:
send the data in one or more transmission cycles, wherein a given transmission cycle is of variable length and includes a least one send slot for each of a plurality of 10SPE network nodes to send data;
delay transmission of data in a first send slot in a first transmission cycle until a second send slot based upon a bandwidth sharing scheme, wherein the circuitry is further configured to delay transmission of data in the first send slot based upon a count of transmission cycles;
delay transmission of data in the first send slot based upon a credit accounting scheme, wherein sending data costs a plurality of credits and credits accrue over time.
2. The 10SPE network node of claim 1 , wherein the circuitry is further configured to delay transmission of data in the first send slot based upon a count of send slots for the 10SPE network node.
3. The 10SPE network node of claim 1 , wherein the transmission cycle includes a plurality of send slots of the 10SPE network.
4. The 10SPE network node of claim 1 , wherein the first send slot and a second slot are of different sizes.
5. The 10SPE network node of claim 1 , wherein the circuitry is further configured to delay transmission of data in the first send slot until the second send slot based upon another 10SPE network node previously sending data.
6. The 10SPE network node of claim 1 , wherein the circuitry is further configured to delay transmission of data in the first send slot until the second send slot based upon the 10SPE network node having a lower priority than one of the other nodes.
7. The 10SPE network node of claim 1 , wherein the instructions are further configured to cause the processor to a delay of transmission of data in a first send slot in a first transmission cycle until the second send slot based upon a determination of inactivity at the other nodes.
8. The 10SPE network node of claim 1 , wherein the circuitry is implemented by instructions to be executed by the processor.
9. A method, comprising:
generate data to be sent to other nodes;
sending the data in one or more transmission cycles, wherein a given transmission cycle is of variable length and includes a least one send slot for each of a plurality of 10SPE network nodes to send data;
delaying transmission of data in a first send slot in a first transmission cycle until a second send slot based upon a bandwidth sharing scheme, based upon a count of transmission cycles; and
delaying transmission of data in the first send slot based upon a credit accounting scheme, wherein sending data costs a plurality of credits and credits accrue over time.
10. The method of claim 9 , further comprising delaying transmission of data in the first send slot based upon a count of sending slots for the 10SPE network node.
11. The method of claim 9 , wherein the transmission cycle includes a plurality of send slots of the 10SPE network.
12. The method of claim 9 , wherein the first send slot and a second slot are of different sizes.
13. The method of claim 9 , further comprising delaying transmission of data in the first send slot until the second send slot based upon another 10SPE network node previously sending data.
14. The method of claim 9 , further comprising delaying transmission of data in the first send slot until the second send slot based upon the 10SPE network node having a lower priority than one of the other nodes.
15. The method of claim 9 , further comprising delaying of transmission of data in a first send slot in a first transmission cycle until the second send slot based upon a determination of inactivity by the other nodes.
16. The method of claim 9 , wherein the method is implemented by instructions to be executed by a processor.