Three-dimensional memory device with logic signal routing through a memory die and methods of making the same

1. A memory device comprising:

a memory die comprising memory elements;

a support die comprising peripheral devices, wherein the support die is bonded to the memory die; and

an electrically conductive path between two of the peripheral devices extends at least partially through the memory die, wherein the electrically conductive path is electrically isolated from the memory elements,

wherein:

the memory elements comprise at least one three-dimensional array of memory elements;

the memory die further comprises memory-die interconnect dielectric layers including memory-die metal interconnect structures, and first memory-die bonding pads that are located on or within the memory-die interconnect dielectric layers and electrically connected to a respective node of the at least one three-dimensional array of memory elements through a first subset of the memory-die metal interconnect structures;

the support die further comprises at least one peripheral circuitry containing the peripheral devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and comprising first support-die bonding pads bonded to the first memory-die bonding pads and electrically connected to a respective node of the at least one peripheral circuitry through a first subset of support-die metal interconnect structures within the support die;

the electrically conductive path is electrically isolated from the at least one three-dimensional array of memory elements is located in the memory-die interconnect dielectric layers;

the electrically conductive path comprises a pair of second memory-die bonding pads that are located on or within the memory-die interconnect dielectric layers, metal via structures contacting a respective one of the pair of second memory-die bonding pads, and a metal line contacting the metal via structures; and

each pair of second memory-die bonding pads is bonded to a respective pair of second support-die bonding pads that are electrically connected to a respective node of the at least one peripheral circuitry through a second subset of support-die metal interconnect structures within the support die.

2. The memory device of claim 1 , wherein the electrically conductive path is electrically isolated from the first subset of the memory-die metal interconnect structures, and wherein each metal line within the electrically conductive path is spaced from an interface between the memory die and the support die.

3. The memory device of claim 1 , wherein:

the at least one three-dimensional array of memory elements comprises a plurality of three-dimensional arrays of memory elements; and

a metal line within the electrically conductive path laterally extends from a first region of the memory-die interconnect dielectric layers located between a first three-dimensional array of memory elements among the plurality of three-dimensional arrays of memory elements and an interface between the memory die and the support die and a second region of the memory-die interconnect dielectric layers located between a second three-dimensional array of memory elements among the plurality of three-dimensional arrays of memory elements and the interface between the memory die and the support die.

4. The memory device of claim 3 , wherein:

the memory die comprises a plurality of planes configured to simultaneously execute a plurality of external commands;

the first three-dimensional array of memory elements is located within a first plane among the plurality of planes; and

the second three-dimensional array of memory elements is located within a second plane among the plurality of planes.

5. The memory device of claim 3 , wherein:

the first three-dimensional array of memory elements comprises a first two-dimensional array of vertical NAND strings extending through a first alternating stack of first insulating layers and first electrically conductive layers located within the memory die; and

the second three-dimensional array of memory elements comprises a second two-dimensional array of vertical NAND strings extending through a second alternating stack of second insulating layers and second electrically conductive layers located within the memory die and laterally spaced from the first two-dimensional array of vertical NAND strings by a dielectric material portion.

6. The memory device of claim 5 , further comprising:

first bit lines electrically connected to a respective subset of vertical NAND strings within the first two-dimensional array of vertical NAND strings and located between the first two-dimensional array of vertical NAND strings and the interface between the memory die and the support die; and

second bit lines electrically connected to a respective subset of vertical NAND strings within the second two-dimensional array of vertical NAND strings, located between the second two-dimensional array of vertical NAND strings and the interface between the memory die and the support die, and electrically isolated from the first bit lines,

wherein the metal line is located between the interface between the memory die and the support die and a collection of the first bit lines and the second bit lines.

7. The memory device of claim 3 , wherein the at least one peripheral circuitry comprises a plurality of peripheral circuitries configured to control operation of a respective one of the plurality of three-dimensional arrays of memory elements.

8. The memory device of claim 7 , wherein:

a first support circuitry region including a first support circuitry among the plurality of peripheral circuitries faces the first region of the memory-die interconnect dielectric layers;

a second support circuitry region including a second support circuitry among the plurality of peripheral circuitries faces the second region of the memory-die interconnect dielectric layers;

a node of the first support circuitry is electrically connected to the metal line; and

a node of the second support circuitry is electrically connected to the metal line.

9. The memory device of claim 8 , wherein:

the metal line is configured to transmit at least one control signal between the node of the first support circuitry and the node of the second support circuitry;

the plurality of three-dimensional arrays of memory elements are provided within a plurality of planes configured to simultaneously execute a plurality of external commands; and

the at least one control signal controls simultaneous execution of two external commands among the plurality of external commands in two planes among the plurality of planes that are controlled by the first support circuitry and by the second support circuitry.

10. The memory device of claim 1 , wherein each of the at least one peripheral circuitry comprises:

sense amplifier and bit line driver circuits;

word line driver circuits;

word line decoder circuits;

source power supply circuits; and

well bias voltage supply circuits.

11. The memory device of claim 1 , further comprising:

through-substrate via structures extending through a substrate of the support die, wherein the at least one peripheral circuitry is located on a first side of the substrate; and

external bonding pads located on a second side of the substrate and contacting a respective one of the through-substrate via structures.

12. A method of operating the memory device of claim 1 , comprising providing an electrical signal between the two of the peripheral devices through the electrically conductive path without passing through the memory elements.

13. A method for forming a memory device, comprising:

providing a memory die comprising memory elements and an interconnect which is electrically isolated from the memory elements;

providing a support die comprising peripheral devices; and

bonding the memory die to the support die such that an electrically conductive path between two of the peripheral devices includes the interconnect,

wherein:

the memory elements comprise at least one three-dimensional array of memory elements;

the memory die further comprises memory-die interconnect dielectric layers including memory-die metal interconnect structures, and first memory-die bonding pads that are located on or within the memory-die interconnect dielectric layers and electrically connected to a respective node of the at least one three-dimensional array of memory elements through a first subset of the memory-die metal interconnect structures, wherein the interconnect is provided in the memory-die interconnect dielectric layers, the electrically conductive path is electrically isolated from the at least one three-dimensional array of memory elements, and the electrically conductive path comprises a pair of second memory-die bonding pads that are located on or within the memory-die interconnect dielectric layers, metal via structures contacting a respective one of the pair of second memory-die bonding pads, and a metal line contacting the metal via structures;

the support die comprises at least one peripheral circuitry containing the peripheral devices configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements, wherein the support die comprises first support-die bonding pads electrically connected to a respective node of the at least one peripheral circuitry through a first subset of support-die metal interconnect structures within the support die; and

the first support-die bonding pads are bonded to the first memory-die bonding pads during bonding; and

each pair of second memory-die bonding pads is bonded to a respective pair of second support-die bonding pads that are electrically connected to a respective node of the at least one peripheral circuitry through a second subset of support-die metal interconnect structures within the support die.

14. The method of claim 13 , wherein:

the electrically conductive path is electrically isolated from the first subset of the memory-die metal interconnect structures;

the at least one three-dimensional array of memory elements comprises a plurality of three-dimensional arrays of memory elements; and

a metal line within the electrically conductive path laterally extends from a first region of the memory-die interconnect dielectric layers located between a first three-dimensional array of memory elements among the plurality of three-dimensional arrays of memory elements and an interface between the memory die and the support die and a second region of the memory-die interconnect dielectric layers located between a second three-dimensional array of memory elements among the plurality of three-dimensional arrays of memory elements and the interface between the memory die and the support die.

15. The method of claim 14 , wherein:

the memory die comprises a plurality of planes configured to simultaneously execute a plurality of external commands;

the first three-dimensional array of memory elements is located within a first plane among the plurality of planes; and

the second three-dimensional array of memory elements is located within a second plane among the plurality of planes.

16. The method of claim 14 , wherein:

the first three-dimensional array of memory elements comprises a first two-dimensional array of vertical NAND strings extending through a first alternating stack of first insulating layers and first electrically conductive layers located within the memory die; and

the second three-dimensional array of memory elements comprises a second two-dimensional array of vertical NAND strings extending through a second alternating stack of second insulating layers and second electrically conductive layers located within the memory die and laterally spaced from the first two-dimensional array of vertical NAND strings by a dielectric material portion.

17. The method of claim 14 , wherein the memory die comprises:

first bit lines electrically connected to a respective subset of vertical NAND strings within the first two-dimensional array of vertical NAND strings and located between the first two-dimensional array of vertical NAND strings and the interface between the memory die and the support die; and

second bit lines electrically connected to a respective subset of vertical NAND strings within the second two-dimensional array of vertical NAND strings, located between the second two-dimensional array of vertical NAND strings and the interface between the memory die and the support die, and electrically isolated from the first bit lines,

wherein the metal line is located between the interface between the memory die and the support die and a collection of the first bit lines and the second bit lines.

18. The method of claim 14 , wherein:

the at least one peripheral circuitry comprises a plurality of peripheral circuitries configured to control operation of a respective one of the plurality of three-dimensional arrays of memory elements;

a first support circuitry region including a first support circuitry among the plurality of peripheral circuitries faces the first region of the memory-die interconnect dielectric layers after bonding the memory die with the support die;

a second support circuitry region including a second support circuitry among the plurality of peripheral circuitries faces the second region of the memory-die interconnect dielectric layers after bonding the memory die with the support die;

a node of the first support circuitry is electrically connected to the metal line; and

a node of the second support circuitry is electrically connected to the metal line.