LUT-based focused ion beam friendly fill-cell design
View Patent ↗An integrated circuit includes a plurality of logic function circuits disposed on the integrated circuit and interconnected by metal interconnect lines to form a logic network. A plurality of configurable logic function circuits is also disposed on the integrated circuit, each configurable logic function circuit being disposed on a respective area on the integrated circuit and not interconnected by the metal interconnect lines to form the logic network.
1. An integrated circuit comprising:
a plurality of logic function circuits disposed on the integrated circuit and interconnected by metal interconnect lines to form a logic network;
a plurality of multiplexer-based lookup tables having a plurality of inputs formed from metal interconnect lines on a first metal interconnect layer, each multiplexer-based lookup table (LUT) disposed on a respective area on the integrated circuit and including a plurality of select inputs and an output, each of the plurality of select inputs and the output being electrically isolated from the plurality of logic function circuits;
each of the inputs of the multiplexer-based lookup tables forming intersections with a VSS rail formed from metal interconnect lines on a metal interconnect layer different from the first metal interconnect layer, each of the inputs of the multiplexer-based lookup tables connected to the VSS rail at the intersections by metal vias; and
each of the inputs of the multiplexer-based lookup tables forming intersections with a VDD rail, the VDD rail formed from metal interconnect lines on a metal interconnect layer different from the first metal interconnect layer.
2. The integrated circuit of claim 1 wherein each multiplexer-based LUT includes four inputs.
3. The integrated circuit of claim 1 wherein each of the plurality of inputs of each multiplexer-based LUT is connected to a metal line in the integrated circuit.
4. A method for performing repairing a logic design error in an integrated circuit including a plurality of logic function circuits disposed on an integrated circuit and interconnected by metal interconnect lines to form a logic network, the method comprising:
providing on the integrated circuit a plurality of multiplexer-based lookup tables having a plurality of inputs formed from metal interconnect lines on a first metal interconnect layer, each multiplexer-based lookup table disposed on a respective area on the integrated circuit and including a plurality of select inputs and an output, each of the plurality of select inputs and the output being electrically isolated from the plurality of logic function circuits, each of the inputs of the multiplexer-based lookup tables forming intersections with a VSS rail formed from metal interconnect lines on a metal interconnect layer different from the first metal interconnect layer, each of the inputs of the multiplexer-based lookup tables connected to the VSS rail at the intersections by metal vias, each of the inputs of the multiplexer-based lookup tables forming intersections with a VDD rail, the VDD rail formed from metal interconnect lines on a metal interconnect layer different from the first metal interconnect layer;
identifying the logic design error by logic type and position on the integrated circuit of the logic function circuit where the deign error is located;
identifying the location of at least one metal interconnect conductor that must be severed to correct the logic design error;
directing a focused ion beam to the location of the at least one metal interconnect conductor and severing the at least one metal interconnect conductor;
identifying a multiplexer-based lookup table having a location nearest to the logic function circuit where the design error is located;
configuring the identified multiplexer-based lookup table to perform a logic function that corrects the logic type of the logic design error; and
connecting the identified multiplexer-based lookup table into the logic network to correct the design error.
5. The method of claim 4 wherein configuring the identified multiplexer-based lookup table to perform the logic function that corrects the logic type of the logic design error comprises:
selectively destroying selected ones of the metal vias to disconnect selected ones of the plurality of inputs from the VSS rail; and
reconnecting the disconnected ones of the plurality of inputs to the VDD rail.
6. The method of claim 5 wherein destroying selected ones of the metal vias to disconnect selected ones of the plurality of inputs from the VSS rail comprises using a focused ion beam to destroy the metal vias connecting the ones of the plurality of inputs to the first metal line.
7. The method of claim 4 wherein:
the multiplexer-based lookup table has at least one select input and one output; and
connecting the identified configurable logic circuit into the logic network to correct the design error comprises connecting the multiplexer-based LUT into the logic network in place of the severed at least one metal interconnect conductor.