3D semiconductor device with isolation layers
A 3D semiconductor device, the device including: a first level including single crystal first transistors, where the first level is overlaid by a first isolation layer; a second level including single crystal second transistors, where the first isolation layer is overlaid by the second level, and where the second level is overlaid by a second isolation layer; a third level including single crystal third transistors, where the second isolation layer is overlaid by the third level, where the third level is overlaid by a third isolation layer, and where the first isolation layer and the second isolation layer are separated by a distance of less than four microns.
1. A 3D semiconductor device, the device comprising:
a first level comprising single crystal first transistors,
wherein said first level is overlaid by a first isolation layer;
a second level comprising single crystal second transistors,
wherein said first isolation layer is overlaid by said second level, and
wherein said second level is overlaid by a second isolation layer;
a third level comprising single crystal third transistors,
wherein said second isolation layer is overlaid by said third level,
wherein said third level is overlaid by a third isolation layer, and
wherein said first isolation layer and said second isolation layer are separated by a distance of less than four microns.
2. The device according to claim 1 ,
wherein said distance is less than two microns.
3. The device according to claim 1 , further comprising:
a connective path between said third transistors and said second transistors,
wherein said connective path comprises a via through said second isolation, and
wherein said via has a diameter of less than 400 nm.
4. The device according to claim 1 , further comprising:
a heat removal path from said second transistors to an external surface of said device.
5. The device according to claim 1 , further comprising:
a power delivery path to said second transistors,
wherein at least a portion of said power delivery path is underneath at least one of said second transistors.
6. The device according to claim 1 ,
wherein misalignment between said third transistors and said second transistors is less than 100 nm.
7. The device according to claim 1 , further comprising:
first connections to external devices; and
second connections to external devices,
wherein at least a portion of said first connections are underneath said first isolation layer, and
wherein at least a portion of said second connections are above said third isolation layer.
8. A 3D semiconductor device, the device comprising:
a first level comprising single crystal first transistors,
wherein said first level is overlaid by a first isolation layer;
a second level comprising single crystal second transistors,
wherein said first isolation layer is overlaid by said second level, and
wherein said second level is overlaid by a second isolation layer;
a third level comprising single crystal third transistors,
wherein said second isolation layer is overlaid by said third level,
wherein said third level is overlaid by a third isolation layer; and
a connective path from said third transistors to said second transistors,
wherein said connective path comprises a via through said second isolation, and
wherein said via has a diameter of less than 400 nm.
9. The device according to claim 8 ,
wherein said first isolation layer and said second isolation layer are separated by a distance of less than two microns.
10. The device according to claim 8 ,
wherein a majority of said second level comprises memory.
11. The device according to claim 8 , further comprising:
a heat removal path from said second transistors to an external surface of said device.
12. The device according to claim 8 , further comprising:
a power delivery path to said second transistors,
wherein at least a portion of said power delivery path is underneath at least one of said second transistors.
13. The device according to claim 8 ,
wherein misalignment between said third transistors and said second transistors is less than 100 nm.
14. The device according to claim 8 , further comprising:
first connections to at least one external device; and
second connections to at least one external device,
wherein at least a portion of said first connections are underneath said first isolation layer, and
wherein at least a portion of said second connections are above said third isolation layer.
15. A 3D semiconductor device, the device comprising:
a first level comprising single crystal first transistors,
wherein said first level is overlaid by a first isolation layer;
a second level comprising single crystal second transistors,
wherein said first isolation layer is overlaid by said second level, and
wherein said second level is overlaid by a second isolation layer;
a third level comprising single crystal third transistors,
wherein said second isolation layer is overlaid by said third level,
wherein said third level is overlaid by a third isolation layer, and
wherein misalignment between said third transistors and said second transistors is less than 100 nm.
16. The device according to claim 15 ,
wherein said first isolation layer and said second isolation layer are separated by a distance of less than four microns.
17. The device according to claim 15 , further comprising:
a connective path from said third transistors to said second transistors,
wherein said connective path comprises a via through said second isolation, and
wherein said via has a diameter of less than 400 nm.
18. The device according to claim 15 , further comprising:
a heat removal path from said second transistors to an external surface of said device.
19. The device according to claim 15 , further comprising:
a power delivery path to said second transistors,
wherein at least a portion of said power delivery path is underneath at least one of said second transistors.
20. The device according to claim 15 , further comprising:
first connections to at least one external device; and
second connections to at least one external device,
wherein at least a portion of said first connections are underneath said first isolation layer, and
wherein at least a portion of said second connections are above said third isolation layer.