Adjustable current sink to draw compensation current from high voltage generation circuitry during programming operation of analog neural memory in deep learning artificial neural network
Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Compensation measures are utilized to compensate for changes in voltage or current as the number of cells being programmed changes.
1. A system for compensating for changes in current applied to a memory array during a programming operation, the system comprising:
an array of non-volatile memory cells;
a high voltage generator for generating a high voltage;
a high voltage buffer for receiving the high voltage from the high voltage generator and outputting the high voltage;
a high voltage decoder for receiving the high voltage from the high voltage buffer and applying the high voltage to a selected set of the non-volatile memory cells in the array during a programming operation; and
an adjustable current sink coupled to the high voltage buffer for drawing a compensation current, wherein the adjustable current sink is adjusted to alter the compensation current when the load on the high voltage buffer changes.
2. The system of claim 1 , wherein the compensation current is proportional to the number of cells to be programmed.
3. The system of claim 1 , wherein the memory array is a vector-by-matrix multiplication array.
4. The system of claim 2 , wherein the memory array is a vector-by-matrix multiplication array.
5. The system of claim 1 , wherein the non-volatile memory cells are split-gate flash memory cells.
6. A method for compensating for changes in current applied to an array of non-volatile memory cells during a programming operation, the method comprising:
generating, by a high voltage generator, a high voltage;
receiving, by a high voltage buffer, the high voltage from the high voltage generator;
receiving, by a high voltage decoder, the high voltage from the high voltage buffer;
applying, by the high voltage decoder, the high voltage to a selected set of non-volatile memory cells in the array during a programming operation;
configuring an adjustable current sink to draw a compensation current in proportion to a load on the high voltage buffer; and
drawing, by the adjustable current sink, the compensation current from the high voltage buffer.
7. The method of claim 6 , wherein the load is proportional to the number of cells to be programmed.
8. The method of claim 6 , wherein the array is a vector-by-matrix multiplication array.
9. The system of claim 7 , wherein the array is a vector-by-matrix multiplication array.
10. The system of claim 6 , wherein the non-volatile memory cells are split-gate flash memory cells.
11. A system for compensating for changes in current applied to a memory array during a programming operation, the system comprising:
an array of non-volatile memory cells;
a high voltage generator for generating a high voltage;
a high voltage buffer for receiving the high voltage from the high voltage generator and outputting the high voltage;
a high voltage decoder for receiving the high voltage from the high voltage buffer and applying the high voltage to a selected set of the non-volatile memory cells in the array during a programming operation; and
an adjustable current sink coupled to the high voltage decoder for drawing a compensation current, wherein the adjustable current sink is adjusted to alter the compensation current when the load on the high voltage decoder changes.
12. The system of claim 11 , wherein the compensation current is proportional to the number of cells to be programmed.
13. The system of claim 11 , wherein the memory array is a vector-by-matrix multiplication array.
14. The system of claim 12 , wherein the memory array is a vector-by-matrix multiplication array.
15. The system of claim 11 , wherein the non-volatile memory cells are split-gate flash memory cells.
16. A method for compensating for changes in current applied to an array of non-volatile memory cells during a programming operation, the method comprising:
generating, by a high voltage generator, a high voltage;
receiving, by a high voltage buffer, the high voltage from the high voltage generator;
receiving, by a high voltage decoder, the high voltage from the high voltage buffer;
applying, by the high voltage decoder, the high voltage to a selected set of non-volatile memory cells in the array during a programming operation;
configuring an adjustable current sink to draw a compensation current in proportion to a load on the high voltage decoder; and
drawing, by the adjustable current sink, the compensation current from the high voltage decoder.
17. The method of claim 16 , wherein the load is proportional to the number of cells to be programmed.
18. The method of claim 16 , wherein the array is a vector-by-matrix multiplication array.
19. The method of claim 17 , wherein the array is a vector-by-matrix multiplication array.
20. The method of claim 16 , wherein the non-volatile memory cells are split-gate flash memory cells.