Split gate non-volatile memory cells and logic devices with FINFET structure, and method of making same
A semiconductor substrate having an upper surface with a plurality of upwardly extending fins. A memory cell formed on a first of the fins and including spaced apart source and drain regions in the first fin, with a channel region extending therebetween along top and side surfaces of the first fin, a floating gate that extends along a first portion of the channel region, a select gate that extends along a second portion of the channel region, a control gate that extends along and is insulated from the floating gate, and an erase gate that extends along and is insulated from the source region. A logic device formed on a second of the fins and including spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending therebetween, and a logic gate that extends along the logic channel region.
1. A memory device, comprising:
a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins includes first and second side surfaces that oppose each other and that terminate in a top surface;
a memory cell formed on a first fin of the plurality of fins, comprising:
spaced apart source and drain regions in the first fin, with a channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and drain regions,
a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,
a select gate that extends along a second portion of the channel region, wherein the select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,
a control gate that extends along and is insulated from the floating gate, and
an erase gate that extends along and is insulated from the source region;
a logic device formed on a second fin of the plurality of fins, comprising:
spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the logic source and drain regions, and
a logic gate that extends along the logic channel region, wherein the logic gate extends along and is insulated from the first and second side surfaces and the top surface of the second fin;
wherein the first and second fins are formed as a single continuous fin.
2. A memory device, comprising:
a semiconductor substrate having an upper surface with a plurality of upwardly extending fins, wherein each of the fins includes first and second side surfaces that oppose each other and that terminate in a top surface;
a memory cell formed on a first fin of the plurality of fins, comprising:
spaced apart source and drain regions in the first fin, with a channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and drain regions,
a floating gate that extends along a first portion of the channel region, wherein the floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,
a select gate that extends along a second portion of the channel region, wherein the select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,
a control gate that extends along and is insulated from the floating gate, and
an erase gate that extends along and is insulated from the source region;
a logic device formed on a second fin of the plurality of fins, comprising:
spaced apart logic source and logic drain regions in the second fin, with a logic channel region of the second fin extending along the top surface and the opposing side surfaces of the second fin between the logic source and drain regions, and
a logic gate that extends along the logic channel region, wherein the logic gate extends along and is insulated from the first and second side surfaces and the top surface of the second fin;
wherein the first and second fins are formed as separate, discrete fins, and wherein the second fin extends higher than the first fin relative to the substrate.
3. The memory device of claim 2 , wherein the erase gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin, and extends along and is insulated from an upper edge of the floating gate.
4. The memory device of claim 3 , wherein the erase gate includes a notch facing the upper edge of the floating gate.
5. The memory device of claim 2 , wherein the logic gate includes a metal material, and wherein the logic gate is insulated from the first and second side surfaces and the top surface of the second fin by a high K insulation material.
6. The memory device of claim 5 , wherein the floating gate, the select gate, the control gate, and the erase gate each include polysilicon material.
7. The memory device of claim 2 , further comprising:
a second logic device formed on a third fin of the plurality of fins, comprising:
spaced apart second logic source and logic drain regions in the third fin, with a second logic channel region of the third fin extending along the top surface and the opposing side surfaces of the third fin between the second logic source and drain regions, and
a second logic gate that extends along the second logic channel region, wherein the second logic gate extends along and is insulated from the first and second side surfaces and the top surface of the third fin.
8. The memory device of claim 7 , wherein:
the logic gate is insulated from the second fin by first insulation material;
the second logic gate is insulated from the third fin by second insulation material;
the first insulation material has a thickness that is greater than that of the second insulation material.
9. The memory device of claim 2 , further comprising:
a second memory cell formed on the first fin, comprising:
a second drain region spaced apart from the source region in the first fin, with a second channel region of the first fin extending along the top surface and the opposing side surfaces of the first fin between the source and second drain regions,
a second floating gate that extends along a first portion of the second channel region, wherein the second floating gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,
a second select gate that extends along a second portion of the second channel region, wherein the second select gate extends along and is insulated from the first and second side surfaces and the top surface of the first fin,
a second control gate that extends along and is insulated from the second floating gate, and
a second erase gate that extends along and is insulated from the source region.