Single event upset immune flip-flop utilizing a small-area highly resistive element
An SEU immune flip-flop includes a master stage data latch having an input, an output, a clock input, being transparent in response to a clock signal first state and being latched in response to a clock signal second state, a slave stage data latch having an input coupled to the master stage data latch output, an output, a scan output, a slave latch clock input, a scan slave latch having an input coupled to the slave stage data latch scan output, an output, and a clock input, being transparent in response to the clock signal second state and being latched in response to the clock signal first state. The slave stage data latch includes a switched inverter disabled when the slave latch is in a transparent state and enabled when the slave latch is in a latched state having a time delay longer than an SEU time period.
1. A single event upset (SEU) immune flip-flop comprising:
a clock line configured to supply a clock signal;
a master stage data latch having a data input, a data output, and a clock input coupled to the clock line, the master stage data latch assuming a transparent state in response to a first state of the clock signal and a latched state in response to a second state of the clock signal;
a slave stage data latch having a data input coupled to the data output of the master stage data latch, a data output, a scan output, and a slave latch clock input;
a scan slave data latch having a data input coupled to the scan output of the slave stage data latch, a data output, and a clock input coupled to the clock line, the scan slave data latch assuming a transparent state in response to the second state of the clock signal and a latched state in response to the first state of the clock signal; and
a slave latch clock line configured to supply a slave clock signal to the slave latch clock input of the slave stage data latch, the slave stage data latch having a transparent state in response to a first state of the slave clock signal and a latched state in response to a second state of the slave clock signal,
wherein the slave stage data latch includes:
a switched inverter having an input node and an output node, the switched inverter in a disabled state when the slave stage data latch is in the transparent state and in an enabled state when the slave stage data latch is in the latched state, the switched inverter formed from switch transistors and inverter transistors; and
a time delay regenerative feedback circuit coupled between the input node of the switched inverter and the output node of the switched inverter, the time delay regenerative feedback circuit forming an RC network when the switched inverter is in its enabled state, the RC network providing a time delay longer than a time period of an SEU event.
2. The SEU immune flip-flop of claim 1 further comprising:
a set signal line; and
wherein the master stage data latch and the scan slave data latch each include a set input coupled to the set signal line.
3. The SEU immune flip-flop of claim 1 further comprising:
a reset signal line; and
wherein the master stage data latch and the scan slave data latch each include a reset input coupled to the reset signal line.
4. The SEU immune flip-flop of claim 1 further comprising:
a multiplexer having a first data input coupled to a data signal line, a second data input coupled to a scan input signal line, a data output coupled to the data input of the master stage data latch, and a select input coupled to an input select signal.
5. The SEU immune flip-flop of claim 1 wherein the slave stage data latch has a data output coupled to the output node of the switched inverter.
6. The SEU immune flip-flop of claim 1 wherein the RC network includes a vertical resistive element and a capacitive element, the capacitive element comprising gate capacitances of the inverter transistors in the switched inverter, the vertical resistive element connected in series with the capacitive element.
7. The SEU immune flip-flop of claim 6 wherein the vertical resistive element is formed as an unprogrammed antifuse.
8. The SEU immune flip-flop of claim 6 wherein the vertical resistive element is formed as a virgin ReRAM device.
9. The SEU immune flip-flop of claim 6 wherein the vertical resistive element is formed as a layer of a high-resistance metal compound.
10. The SEU immune flip-flop of claim 9 wherein the high-resistance metal compound is one of silicon-rich SiO 2 , tantalum-rich Ta 2 O 5 , titanium-rich TiO 2 , aluminum-rich Al 2 O 3 , and silicon-rich SiN.
11. The SEU immune flip-flop of claim 1
wherein the switched inverter switch transistors and inverter transistors comprise:
a p-channel inverter transistor connected in series with a p-channel switching transistor between a first voltage supply node and the switched inverter output node, a gate of the p-channel inverter transistor connected to the switched inverter input node;
an n-channel inverter transistor connected in series with an n-channel switching transistor between the inverter output node and a second voltage supply node, a gate of the n-channel inverter transistor connected to the switched inverter input node, and
wherein the time delay regenerative feedback circuit comprises a first inverter whose input is connected to the switched inverter output node and whose output is connected in series with the RC network, the RC network including a vertical resistive element coupled to the switched inverter input node, the provided time delay being a function of a resistance of the vertical resistive element and a capacitor comprising the capacitances of the gates of the p-channel inverter transistor and the re-channel inverter transistor.
12. The SEU immune flip-flop of claim 11 , further comprising a second inverter connected between an output of the first inverter and the scan output of the slave stage data latch.
13. The SEU immune flip-flop of claim 12 , further comprising a third inverter connected between an output of the first inverter and an output node of the SEU immune flip-flop.
14. A single event upset (SEU) immune flip-flop comprising:
a clock line configured to supply a clock signal;
a master stage data latch having a data input, a data output, and a clock input coupled to the clock line, the master stage data latch assuming a transparent state in response to a first state of the clock signal and a latched state in response to a second state of the clock signal;
a slave stage data latch having a data input coupled to the data output of the master stage data latch, a data output, a scan output, and a slave latch clock input;
a scan slave data latch having a data input coupled to the scan output of the slave stage data latch, a data output, and a clock input coupled to the clock line, the scan slave data latch assuming a transparent state in response to the second state of the clock signal and a latched state in response to the first state of the clock signal; and
a slave latch clock line configured to supply a slave clock signal to the slave latch clock input of the slave stage data latch, the slave stage data latch having a transparent state in response to a first state of the slave clock signal and a latched state in response to a second state of the slave clock signal,
wherein the slave stage data latch includes:
a switched inverter having an input node and an output node, the switched inverter in a disabled state when the slave stage data latch is in the transparent state and in an enabled state when the slave stage data latch is in the latched state, the switched inverter formed from switch transistors and inverter transistors; and
a time delay regenerative feedback circuit coupled between the input node of the switched inverter and the output node of the switched inverter, the time delay regenerative feedback circuit including a vertical resistive element,
wherein the vertical resistive element forms an RC network when the switched inverter is in its enabled state, the RC network including a capacitive element connected in series with the vertical resistive element, the capacitive element comprising the gate capacitances of the inverter transistors.