Self-biased non-isolated low-power switching regulator
View Patent ↗A self-biased non-isolated buck regulator is provided. The regulator may include a first input terminal and a second input terminal, a high-voltage switch coupled to the first input terminal, a low-voltage switch coupled to the high-voltage switch, an inductor having a first terminal coupled to the high-voltage switch and the first low-voltage switch, a high-voltage rectifier diode coupled between the first low-voltage switch and the second input terminal, a second low-voltage switch coupled to the first low-voltage switch and the high-voltage rectifier diode, and a capacitor having a first terminal coupled to the first terminal of the inductor, and a second terminal coupled to the second low-voltage switch.
1. A regulator comprising:
a first input terminal and a second input terminal for receiving input voltage;
a high-voltage switch coupled to the first input terminal;
a first low-voltage switch coupled to the high-voltage switch;
an inductor having a first terminal coupled to the high-voltage switch and the first low-voltage switch;
a high-voltage rectifier diode coupled between the low-voltage switch and the second input terminal;
a second low-voltage switch coupled to the first low-voltage switch and the high-voltage rectifier diode; and
a capacitor having a first terminal coupled to the first terminal of the inductor, and a second terminal coupled to the second low-voltage switch.
2. The regulator of claim 1 , wherein the second low-voltage switch is a low-voltage diode having an anode and a cathode, wherein the anode of the low-voltage diode is coupled to the first low-voltage switch, and wherein the cathode of the low-voltage diode is coupled to the second terminal of the capacitor.
3. The regulator of claim 1 , wherein the high-voltage switch and first low-voltage switch are field effect transistors (FETs);
wherein a source terminal of the high-voltage switch is coupled to a source terminal of the first low-voltage switch; and
wherein the source terminals of the high-voltage switch and low-voltage switch are coupled to the first terminal of the inductor.
4. The regulator of claim 3 , wherein a drain terminal of the first low-voltage switch is coupled to the high-voltage rectifier diode and the second low-voltage switch.
5. The regulator of claim 1 wherein the first low-voltage switch is configured to be deactivated to facilitate an alternate current path through the second low-voltage switch.
6. The regulator of claim 1 further comprising a current sense element configured to sense current in the first low-voltage switch.
7. The regulator of claim 1 further comprising a comparator configured to monitor a voltage drop across the first low-voltage switch and thereby sense current in the first low-voltage switch.
8. The regulator of claim 1 wherein the high-voltage switch is configured to be activated once current in the first low-voltage switch has reached substantially zero.
9. The regulator of claim 6 further comprising:
a first comparator configured to compare an output of the current sense element and a minimum threshold level.
10. The regulator of claim 1 further comprising:
a second comparator configured to compare a voltage at the first low-voltage switch to a voltage at the capacitor.
11. The regulator of claim 9 further comprising:
a PWM latch coupled to the first low-voltage switch and the first comparator,
wherein the PWM latch is configured to turn off the first low-voltage switch based on an output of the first comparator indicating that the output of the current sense element is less than the minimum threshold level.
12. The regulator of claim 10 further comprising: a PWM latch coupled to the first low-voltage switch and the second comparator wherein the PWM latch is configured to activate the low-voltage switch based on an output of the second comparator indicating that the voltage at the low-voltage switch is less than the voltage at the capacitor.
13. The regulator of claim 6 , further comprising a comparator configured to compare an output of the current sense element and a substantially zero threshold level.
14. The regulator of claim 13 , further comprising a PWM latch coupled to the comparator and the high-voltage switch;
wherein the PWM latch is configured to turn on the high-voltage switch based on an output of the comparator indicating that the current in the low-voltage switch is substantially zero.
15. The regulator of claim 6 , further comprising a comparator configured to compare an output from the current sense element and a maximum threshold level.
16. The regulator of claim 15 , further comprising:
a protection latch coupled to an output of the comparator;
wherein the protection latch is configured to inhibit a gate drive signal from turning on the high-voltage switch based on an output of the comparator indicating that the current in the output of the current sense element is greater than the maximum threshold level.
17. The regulator of claim 16 , further comprising:
a delay timer having an input coupled to the output of the comparator and an output coupled to the protection latch;
wherein the protection latch is configured to enable the gate drive signal to turn on the high-voltage switch based on an output of the delay timer.
18. A regulator comprising:
a first input terminal and a second input terminal for receiving input voltage;
an integrated circuit coupled to the first input terminal;
a high-voltage rectifier diode coupled between the integrated circuit and the second input terminal;
an inductor coupled to an output pin of the integrated circuit; and
a capacitor having a first terminal coupled to the inductor and a second terminal coupled to the integrated circuit;
wherein said integrated circuit comprises:
a high-voltage switch coupled to the first input terminal;
a first low-voltage switch having a source terminal coupled to the high-voltage switch and the inductor, and a drain terminal coupled to the high-voltage rectifier diode; and
a second low-voltage switch coupled between the drain terminal of the first low-voltage switch and the second terminal of the capacitor.
19. The regulator of claim 18 , wherein the second low-voltage switch is a low-voltage diode having an anode and a cathode, wherein the anode of the low-voltage diode is coupled to the first low-voltage switch, and wherein the cathode of the low-voltage diode is coupled to the second terminal of the capacitor.
20. The regulator of claim 18 further comprising a current source coupled between the first input terminal and the second terminal of the capacitor, said current source configured to initially charge the capacitor.
21. The regulator of claim 18 further comprising a resistor coupled to an input pin of the integrated circuit for sensing at least one of a peak voltage potential and an average voltage potential at the output pin of the integrated circuit.