Reusable support substrate for formation and transfer of semiconductor devices and methods of using the same
A support substrate including a plurality of channels on a front side is provided. A cover layer is formed by anisotropically depositing a sacrificial cover material over the plurality of channels. Cavities laterally extend within the plurality of channels underneath a horizontally extending portion of the cover layer. An encapsulation layer is conformally deposited. First semiconductor devices, first metal interconnect structures, and first bonding pads are formed over a top surface of the encapsulation layer. A device substrate with second bonding pads is provided. The second bonding pads are bonded with the first bonding pads to form a bonded assembly. Peripheral portions of the encapsulation layer are removes and peripheral portions of the cover layer are physically exposed. The cover layer is removed employing an isotropic etch process by propagating an isotropic etchant through the cavities to separate the support substrate from the bonded assembly.
1. A method of forming a semiconductor structure, comprising:
providing a support substrate comprising a plurality of channels located on a front side;
forming a cover layer by anisotropically depositing a sacrificial cover material over the plurality of channels, wherein cavities laterally extend within the plurality of channels underneath a horizontally extending portion of the cover layer;
conformally depositing an encapsulation layer on a top surface of the cover layer and on a backside surface of the support substrate;
forming first semiconductor devices, first metal interconnect structures embedded in first dielectric material layers, and first bonding pads over a top surface of the encapsulation layer;
providing a device substrate with second semiconductor devices, second metal interconnect structures embedded in second dielectric material layers, and second bonding pads thereupon;
bonding the second bonding pads with the first bonding pads to form a bonded assembly;
removing peripheral portions of the encapsulation layer, wherein peripheral portions of the cover layer are physically exposed; and
removing the cover layer employing an isotropic etch process by propagating an isotropic etchant through the cavities to separate the support substrate from the bonded assembly.
2. The method of claim 1 , wherein a first assembly of the support substrate and a first portion of the encapsulation layer located on the backside surface of the support substrate is separated from a second assembly of a second portion of the encapsulation layer, the first semiconductor devices, the first metal interconnect structures, the first dielectric material layers, the first bonding pads, the second bonding pads, the second metal interconnect structures, the second dielectric material layers, the second semiconductor devices, and at least a portion of the device substrate.
3. The method of claim 2 , further comprising removing the first portion of the encapsulation layer from the support substrate after the first assembly is separated from the second assembly.
4. The method of claim 3 , further comprising:
forming a second cover layer by anisotropically depositing a sacrificial cover material over the plurality of channels after removing the first portion of the encapsulation layer from the support substrate;
conformally depositing a second encapsulation layer on a top surface of the second cover layer and on a backside surface of the support substrate; and
forming third semiconductor devices, third metal interconnect structures embedded in third dielectric material layers, and third bonding pads over a top surface of the second encapsulation layer.
5. The method of claim 1 , wherein:
the device substrate comprises a silicon substrate including a hydrogen-implanted layer located between a proximal semiconductor layer and a distal semiconductor layer, wherein the proximal semiconductor layer is more proximal to the second semiconductor devices than the distal semiconductor layer is to the second semiconductor devices; and
the method further comprises splitting the distal semiconductor layer from the proximal semiconductor layer by performing an anneal process at an elevated temperature that induces blistering of hydrogen atoms in the hydrogen-implanted layer.
6. The method of claim 5 , wherein the anneal process is performed after bonding the second bonding pads to the first bonding pads.
7. The method of claim 6 , wherein the anneal process is performed after removing the cover layer.
8. The method of claim 1 , further comprising:
removing portions of the first dielectric material layers from a bevel region located in a peripheral region of the support substrate, wherein the peripheral portions of the encapsulation layer are physically exposed;
forming a passivation dielectric spacer on a physically exposed sidewall of the first dielectric material layers by conformally depositing and anisotropically etching a passivation dielectric material, wherein the passivation dielectric spacer protects the first dielectric material layers during removal of the cover layer.
9. The method of claim 8 , wherein:
the passivation dielectric spacer has a tubular configuration and vertically extends from a top surface of an upper portion of the encapsulation layer that overlies the support substrate to a topmost layer within the first dielectric material layers; and
the passivation dielectric spacer comprises silicon nitride.
10. The method of claim 1 , wherein the isotropic etch process comprises a wet etch process that employs a wet etchant that etches a material of the cover layer selective to materials of the support substrate and the encapsulation layer.
11. The method of claim 10 , wherein the cover layer comprises a doped silicate glass or organosilicate glass.
12. The method of claim 11 , wherein the encapsulation layer comprises a dielectric metal oxide material.
13. The method of claim 1 , wherein each channel within the plurality of channels has a depth-to-width ratio in a range from 1 to 100.
14. The method of claim 1 , wherein each channel width the plurality of channels has a depth in a range from 1 micron to 30 microns, and a width in a range from 100 nm to 5 microns.
15. The method of claim 1 , wherein:
the first semiconductor devices comprise a three-dimensional array of memory elements; and
the second semiconductor devices comprise a logic circuit configured to control operation of the three-dimensional array of memory elements.
16. The method of claim 15 , wherein the first semiconductor devices comprise:
an alternating stack of insulating layers and electrically conductive layers; and
a two-dimensional array of vertical NAND strings that vertically extend through the alternating stack, wherein each of the vertical NAND strings comprises a respective vertical semiconductor channel and memory film.
17. The method of claim 1 , wherein the plurality of channels comprises:
first channels that laterally extend straight along a first horizontal direction from a respective first end point at a peripheral region of the support substrate to a respective second end point at a peripheral region of the support substrate; and
second channels that laterally extend straight along a second horizontal direction from a respective first end point at the peripheral region of the support substrate to a respective second end point at a peripheral region of the support substrate and intersecting a respective subset of the first channels.
18. The method of claim 1 , wherein the plurality of channels comprises a plurality of serpentine channels that extend along a first horizontal direction from a respective first end point at a peripheral region of the support substrate to a respective second end point at the peripheral region of the support substrate with a lateral undulation along a second horizontal direction that is perpendicular to the first horizontal direction.
19. The method of claim 1 , wherein the plurality of channels comprises:
radial channels that extend straight radially from a respective first end point at a peripheral region of the support substrate to a respective second end point that is more proximal to a vertical axis passing through a geometrical center of the support substrate than to the peripheral region of the support substrate; and
azimuthal channels that are located at a respective distance from the vertical axis passing through the geometrical center of the support substrate and intersecting a respective subset of the support substrate.