Method to form a 3D semiconductor device and structure
A method to form a 3D semiconductor device, the method including: providing a first wafer including first circuits including transistors and interconnection; preparing a second wafer including a silicon layer; performing growth of an epitaxial layer on top of the silicon layer, the epitaxial layer including non-silicon atoms, forming second circuits over the second wafer, the second circuits including transistors and interconnection; transferring and then bonding the second wafer on top of the first wafer; and then thinning the second wafer to a thickness of less than ten microns.
1. A method to form a 3D semiconductor device, the method comprising:
providing a first wafer comprising first circuits comprising transistors and interconnection;
preparing a second wafer comprising a silicon layer;
performing growth of an epitaxial layer on top of said silicon layer, said epitaxial layer comprising non silicon atoms,
forming second circuits over said second wafer, said second circuits comprising transistors and interconnection;
transferring and then bonding said second wafer on top of said first wafer; and then
thinning said second wafer to a thickness of less than ten microns;
forming an upper most semiconductor level,
wherein said upper most semiconductor level comprises Input/Output (“I/O”) circuits designed to connect said device to external devices, and
wherein said I/O circuits are aligned to said first circuits with less than 200 nm misalignment.
2. A method to form a 3D semiconductor device, the method comprising:
providing a first wafer comprising first circuits comprising transistors and interconnection;
preparing a second wafer comprising a silicon layer;
performing growth of an epitaxial layer on top of said silicon layer, said epitaxial layer comprising non silicon atoms,
forming second circuits over said second wafer, said second circuits comprising transistors and interconnection;
transferring and then bonding said second wafer on top of said first wafer; and then
thinning said second wafer to a thickness of less than ten microns;
wherein said bonding is by hybrid bonding,
wherein said hybrid bonding comprises metal to metal bonds.
3. A method to form a 3D semiconductor device, the method comprising:
providing a first wafer comprising first circuits comprising transistors and interconnection;
preparing a second wafer comprising a silicon layer;
performing growth of an epitaxial layer on top of said silicon layer, said epitaxial layer comprising non silicon atoms,
forming second circuits over said second wafer, said second circuits comprising transistors and interconnection;
transferring and then bonding said second wafer on top of said first wafer; and then
thinning said second wafer to a thickness of less than ten microns;
forming heat removal wires designed to remove heat of said second circuit to the external surface of said 3D semiconductor device.
4. A 3D semiconductor device, the device comprising:
a first level overlaid by a second level, said first level comprising first circuits,
wherein said first circuits comprise first single crystal transistors and comprise first interconnections,
wherein said second level comprises second circuits, said second circuits comprise single crystal second transistors and comprise second interconnections, and
wherein said first circuit is aligned to said second circuit with less than 200 nm misalignment; and
a shielding metal layer designed to protect said first circuit from electromagnetic frequencies (EMF) noise generated by circuits disposed above said shielding metal layer.
5. The 3D semiconductor device according to claim 4 , further comprising:
an upper most semiconductor level,
wherein said upper most semiconductor level comprises Input/Output (“I/O”) circuits designed to connect said device to external devices, and
wherein said I/O circuits are aligned to said first circuits with less than 200 nm misalignment.
6. The 3D semiconductor device according to claim 4 , further comprising:
a Global Power distribution network,
wherein said Global Power distribution network distributes power to at least one Local Power distribution network,
wherein said Global Power distribution network comprises wires comprising an at least 50% greater conductivity than wires of said Local Power distribution network.
7. The 3D semiconductor device according to claim 4 , further comprising:
two layers bonded by hybrid bonding.
8. The 3D semiconductor device according to claim 4 , further comprising:
heat removal wires designed to remove heat of said second circuit to an external surface of said 3D semiconductor device.
9. The 3D semiconductor device according to claim 4 ,
wherein a first operating voltage of said first circuit differs by at least 15% from a second operating voltage of said second circuit.
10. The 3D semiconductor device according to claim 4 ,
wherein said 3D semiconductor device was processed by a method comprising:
preparing a second wafer comprising a silicon base layer,
forming an epitaxial layer on top of said silicon base layer comprising non silicon atoms,
forming second circuits over said second wafer comprising transistors and interconnection,
transferring and then bonding said second wafer on top of a first wafer, and then
thinning said second wafer to thickness of less than ten microns.
11. A 3D semiconductor device, the device comprising:
a first level overlaid by a second level, said first level comprising first circuits,
wherein said first circuits comprise single crystal first transistors and comprise first interconnections,
wherein said second level comprises second circuits, said second circuits comprise single crystal second transistors and comprise second interconnections,
wherein said first circuit is aligned to said second circuit with less than 200 nm misalignment; and
a Global Power distribution network,
wherein said first level comprises at least one Local Power distribution network,
wherein said Global Power distribution network distributes power to said Local Power distribution network,
wherein said Global Power distribution network comprises wires comprising an at least 50% greater conductivity than wires of said Local Power distribution network.
12. The 3D semiconductor device according to claim 11 , further comprising:
an upper most semiconductor level,
wherein said upper most semiconductor level comprises Input/Output (“I/O”) circuits designed to connect said device to at least one external device, and
wherein said I/O circuits are aligned to said first circuits with less than 200 nm misalignment.
13. The 3D semiconductor device according to claim 11 , further comprising:
a shielding metal layer designed to protect said first circuit from electromagnetic frequencies (EMF) noise generated by circuits disposed above said shielding metal layer.
14. The 3D semiconductor device according to claim 11 , further comprising:
two layers bonded by hybrid bonding.
15. The 3D semiconductor device according to claim 11 , further comprising:
heat removal wires designed to remove heat of said second circuit to an external surface of said 3D semiconductor device.
16. The 3D semiconductor device according to claim 11 ,
wherein a first operating voltage of said first circuit differs by at least 15% from a second operating voltage of said second circuit.