System and method for minimizing floating gate to floating gate coupling effects during programming in flash memory
An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.
1. A memory device, comprising:
an array of non-volatile memory cells, wherein each of the non-volatile memory cells includes a floating gate, and
a controller configured to:
identify programming values associated with incoming data, wherein each of the programming values is associated with a relative amount of electrons to be placed onto one of the floating gates;
associate each data of the incoming data with one of a plurality of data groups based on the programming value associated therewith, wherein each of the data groups is associated with a unique programming value or a unique range of programming values;
perform a programming operation in which the data groups of the incoming data are programmed into at least some of the non-volatile memory cells in a timing order of descending value of the unique programming values or the unique range of programming values of the plurality of data groups.
2. The memory device of claim 1 , wherein the plurality of data groups is two data groups.
3. The memory device of claim 1 , wherein the plurality of data groups is equal to a number of data in the incoming data.
4. The memory device of claim 1 , wherein the non-volatile memory cells are arranged in rows and columns, and wherein the plurality of data groups is equal to a number of the non-volatile memory cells in one of the rows of the non-volatile memory cells.
5. The memory device of claim 1 , wherein the non-volatile memory cells are arranged in rows and columns, and wherein the plurality of data groups is equal to a number of the non-volatile memory cells in two of the rows of the non-volatile memory cells.
6. The memory device of claim 1 , wherein the non-volatile memory cells are arranged in rows and columns, and wherein the at least some of the non-volatile memory cells is one of the rows of the non-volatile memory cells.
7. The memory device of claim 1 , wherein the non-volatile memory cells are arranged in rows and columns, and wherein the at least some of the non-volatile memory cells is two of the rows of the non-volatile memory cells.
8. The memory device of claim 1 , wherein the controller is further configured to:
pre-program each of the at least some of the non-volatile memory cells to an intermediate program value before the performing of the programming operation.
9. A method of operating a memory device that includes an array of non-volatile memory cells, wherein each of the non-volatile memory cells includes a floating gate, the method comprising:
identifying programming values associated with incoming data, wherein each of the programming values is associated with a relative amount of electrons to be placed onto one of the floating gates;
associating each data of the incoming data with one of a plurality of data groups based on the programming value associated therewith, wherein each of the data groups is associated with a unique programming value or a unique range of programming values;
performing a programming operation in which the data groups of the incoming data are programmed into at least some of the non-volatile memory cells in a timing order of descending value of the unique programming values or the unique range of programming values of the plurality of data groups.
10. The method of claim 9 , wherein the plurality of data groups is two data groups.
11. The method of claim 9 , wherein the plurality of data groups is equal to a number of data in the incoming data.
12. The method of claim 9 , wherein the non-volatile memory cells are arranged in rows and columns, and wherein the plurality of data groups is equal to a number of the non-volatile memory cells in one of the rows of the non-volatile memory cells.
13. The method of claim 9 , wherein the non-volatile memory cells are arranged in rows and columns, and wherein the plurality of data groups is equal to a number of the non-volatile memory cells in two of the rows of the non-volatile memory cells.
14. The method of claim 9 , wherein the non-volatile memory cells are arranged in rows and columns, and wherein the at least some of the non-volatile memory cells is one of the rows of the non-volatile memory cells.
15. The method of claim 9 , wherein the non-volatile memory cells are arranged in rows and columns, and wherein the at least some of the non-volatile memory cells is two of the rows of the non-volatile memory cells.
16. The method of claim 9 , further comprising:
pre-programming each of the at least some of the non-volatile memory cells to an intermediate program value before the performing of the programming operation.