Semiconductor memory device having bonded first and second semiconductor chips provided with respective impedance calibration control circuits
A method for controlling a memory system, including a controller chip and a non-volatile memory chip which includes a calibration control circuit, a first output buffer, and a first resistance element, includes receiving a read command from the controller, setting a ready/busy signal to a busy state based on the read command, executing a calibration operation which controls an impedance of the first output buffer based on the read command, setting the ready/busy signal to a ready state, and sending data to the control chip in response to the read command. The calibration control circuit calibrates the impedance of the first output buffer circuit by using the first resistance element within a period in which the ready/busy signal is the busy state.
1. A semiconductor device comprising:
a first semiconductor chip including:
a first nonvolatile memory cell;
a first sequencer configured to control an operation of the first nonvolatile memory cell;
a first output buffer circuit configured to output data;
a first calibration control circuit configured to calibrate an impedance of the first output buffer circuit;
a first terminal connected to the first calibration control circuit; and
a first resistance element connected to the first terminal; and
a second semiconductor chip including:
a second nonvolatile memory cell;
a second sequencer configured to control an operation of the second nonvolatile memory cell;
a second output buffer circuit configured to output data;
a second calibration control circuit configured to calibrate an impedance of the second output buffer circuit;
a second terminal connected to the second calibration control circuit; and
a second resistance element connected to the second terminal,
wherein:
the first semiconductor chip and the second semiconductor chip are bonded together and covered with a package material,
when a first read operation is performed for the first nonvolatile memory cell, the first sequencer sets a ready/busy signal to a busy state based on a first read command, and the first calibration control circuit calibrates the impedance of the first output buffer circuit within a period in which the ready/busy signal is set to the busy state and the first output buffer circuit to which a first power supply voltage is supplied does not operate, and
when a second read operation is performed for the second nonvolatile memory cell, the second sequencer sets the ready/busy signal to the busy state based on a second read command, and the second calibration control circuit calibrates the impedance of the second output buffer circuit within a period in which the ready/busy signal is set to the busy state and the second output buffer circuit to which the first power supply voltage is supplied does not operate, independently of the first calibration control circuit.
2. The semiconductor device according to claim 1 , wherein the impedance of the first output buffer circuit is calibrated based on a resistance value of the first resistance element.
3. The semiconductor device according to claim 2 , wherein the impedance of the second output buffer circuit is calibrated based on a resistance value of the second resistance element.
4. The semiconductor device according to claim 1 , wherein the first semiconductor chip further includes a temperature sensor configured to sense a temperature of the first semiconductor chip, and
wherein the temperature sensor controls a resistance value of the first resistance element based on a sense result of sensing the temperature.
5. The semiconductor device according to claim 1 , wherein the first semiconductor chip and the second semiconductor chip are provided above a substrate, and
wherein the first output buffer circuit and the second output buffer circuit are connected in common with a third terminal on the substrate.
6. The semiconductor device according to claim 1 , wherein the first semiconductor chip further includes a third terminal and a first interconnect electrically separated from the third terminal,
wherein a first voltage is supplied to the third terminal, and
wherein a second voltage is supplied to the first output buffer circuit through the first interconnect.
7. The semiconductor device according to claim 6 , wherein the first semiconductor chip further includes a fourth terminal connected to the first interconnect, and
wherein the second voltage is supplied to the fourth terminal.
8. The semiconductor device according to claim 7 , wherein the first semiconductor chip further includes a fifth terminal and a sixth terminal electrically separated from the fifth terminal,
wherein a third voltage lower than the first voltage is supplied to the fifth terminal, and
wherein a fourth voltage lower than the second voltage is supplied to the sixth terminal.
9. The semiconductor device according to claim 1 , wherein the first semiconductor chip comprises a NAND flash memory.