Contact resistance reduction employing germanium overlayer pre-contact metalization
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
1. An integrated circuit structure, comprising:
a fin comprising silicon;
a gate electrode over the fin, the gate electrode having a first side, and the gate electrode having a second side opposite the first side;
a first dielectric spacer along the first side of the gate electrode;
a first source or drain region in the fin proximate the first side of the gate electrode, a portion of the first source or drain region beneath the first dielectric spacer, wherein the first source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a second dielectric spacer along the second side of the gate electrode;
a second source or drain region in the fin proximate the second side of the gate electrode, a portion of the second source or drain region beneath the second dielectric spacer, wherein the second source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a dielectric layer over the first source or drain region and over the second source or drain region, the dielectric layer having a first opening exposing only a portion of the first source or drain region, and the dielectric layer having a second opening exposing only a portion of the second source or drain region;
a first germanide layer in the first opening and over the portion of the first source or drain region, the first germanide layer comprising silicon, germanium and titanium;
a second germanide layer in the second opening and over the portion of the second source or drain region, the second germanide layer comprising silicon, germanium and titanium;
a first contact plug in the first opening and on the first germanide layer; and
a second contact plug in the second opening and on the second germanide layer.
2. The integrated circuit structure of claim 1 , further comprising:
a first boron doped germanium layer on the first source or drain region, wherein the first germanide layer is on the first boron doped germanium layer, and wherein the first boron doped germanium layer has a germanium concentration in excess of 90 atomic % and a boron concentration in excess of 1E20 cm-3; and
a second boron doped germanium layer on the second source or drain region, wherein the second germanide layer is on the second boron doped germanium layer, and wherein the second boron doped germanium layer has a germanium concentration in excess of 90 atomic % and a boron concentration in excess of 1E20 cm-3.
3. The integrated circuit structure of claim 2 , wherein the first boron doped germanium layer is in the first opening of the dielectric layer, and wherein the second boron doped germanium layer is in the second opening of the dielectric layer.
4. The integrated circuit structure of claim 2 , wherein the first boron doped germanium layer is below first opening of the dielectric layer and extends beyond the first opening of the dielectric layer, and wherein the second boron doped germanium layer is below the second opening of the dielectric layer and extends beyond the first opening of the dielectric layer.
5. The integrated circuit structure of claim 1 , further comprising:
an isolation region, wherein the fin protrudes through the isolation region, and wherein a portion of the gate electrode, a portion of the first dielectric spacer, and a portion of the second dielectric spacer are over the isolation region.
6. The integrated circuit structure of claim 1 , further comprising:
a gate dielectric layer, wherein the gate electrode is on the gate dielectric layer, wherein the gate dielectric layer comprises a high-k dielectric material, and wherein the gate electrode comprises a metal layer.
7. The integrated circuit structure of claim 1 , wherein the first source or drain region comprises two or more facets, and the second source or drain region comprises two or more facets.
8. An integrated circuit structure, comprising:
a body comprising silicon;
a gate electrode over the body, the gate electrode having a first side, and the gate electrode having a second side opposite the first side;
a first dielectric spacer along the first side of the gate electrode;
a first source or drain region in the body proximate the first side of the gate electrode, a portion of the first source or drain region beneath the first dielectric spacer, wherein the first source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a second dielectric spacer along the second side of the gate electrode;
a second source or drain region in the body proximate the second side of the gate electrode, a portion of the second source or drain region beneath the second dielectric spacer, wherein the second source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a dielectric layer over the first source or drain region and over the second source or drain region, the dielectric layer having a first opening exposing only a portion of the first source or drain region, and the dielectric layer having a second opening exposing only a portion of the second source or drain region;
a first germanide layer in the first opening and over the portion of the first source or drain region, the first germanide layer comprising silicon, germanium and titanium;
a second germanide layer in the second opening and over the portion of the second source or drain region, the second germanide layer comprising silicon, germanium and titanium;
a first contact plug in the first opening and on the first germanide layer; and
a second contact plug in the second opening and on the second germanide layer.
9. The integrated circuit structure of claim 8 , further comprising:
a first boron doped germanium layer on the first source or drain region, wherein the first germanide layer is on the first boron doped germanium layer, and wherein the first boron doped germanium layer has a germanium concentration in excess of 90 atomic % and a boron concentration in excess of 1E20 cm-3; and
a second boron doped germanium layer on the second source or drain region, wherein the second germanide layer is on the second boron doped germanium layer, and wherein the second boron doped germanium layer has a germanium concentration in excess of 90 atomic % and a boron concentration in excess of 1E20 cm-3.
10. The integrated circuit structure of claim 9 , wherein the first boron doped germanium layer is in the first opening of the dielectric layer, and wherein the second boron doped germanium layer is in the second opening of the dielectric layer.
11. The integrated circuit structure of claim 9 , wherein the first boron doped germanium layer is below first opening of the dielectric layer and extends beyond the first opening of the dielectric layer, and wherein the second boron doped germanium layer is below the second opening of the dielectric layer and extends beyond the first opening of the dielectric layer.
12. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a fin comprising silicon;
a gate electrode over the fin, the gate electrode having a first side, and the gate electrode having a second side opposite the first side;
a first dielectric spacer along the first side of the gate electrode;
a first source or drain region in the fin proximate the first side of the gate electrode, a portion of the first source or drain region beneath the first dielectric spacer, wherein the first source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a second dielectric spacer along the second side of the gate electrode;
a second source or drain region in the fin proximate the second side of the gate electrode, a portion of the second source or drain region beneath the second dielectric spacer, wherein the second source or drain region comprises silicon and germanium having a germanium concentration graded to a concentration in excess of 50%;
a dielectric layer over the first source or drain region and over the second source or drain region, the dielectric layer having a first opening exposing only a portion of the first source or drain region, and the dielectric layer having a second opening exposing only a portion of the second source or drain region;
a first germanide layer in the first opening and over the portion of the first source or drain region, the first germanide layer comprising silicon, germanium and titanium;
a second germanide layer in the second opening and over the portion of the second source or drain region, the second germanide layer comprising silicon, germanium and titanium;
a first contact plug in the first opening and on the first germanide layer; and
a second contact plug in the second opening and on the second germanide layer.
13. The computing device of claim 12 , further comprising:
a memory coupled to the board.
14. The computing device of claim 12 , further comprising:
a communication chip coupled to the board.
15. The computing device of claim 12 , further comprising:
a camera coupled to the board.
16. The computing device of claim 12 , further comprising:
a battery coupled to the board.
17. The computing device of claim 12 , further comprising:
an antenna coupled to the board.
18. The computing device of claim 12 , wherein the component is a packaged integrated circuit die.
19. The computing device of claim 12 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
20. The computing device of claim 12 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.