Timer circuit with autonomous floating of pins and related systems, methods, and devices
An electrical system includes an integrated circuit device including input/output (I/O) pins, a reset circuit, and an I/O circuit. The I/O circuit is operably coupled to the I/O pins. The I/O circuit is configured to selectively operate the I/O pins in an electrically floating state responsive to a system reset signal transmitted by the reset circuit. The I/O circuit is further configured to selectively operate the I/O pins in the electrically floating state responsive to a signal provided by a timer circuit independently from the reset circuit.
1. An electrical system, comprising:
a timer circuit to generate and transmit a plurality of signals; and
an integrated circuit device operatively coupled to the timer circuit, comprising:
a central processing unit (CPU);
input/output (I/O) pins to conduct I/O signals between internal circuitry of the integrated circuit device and a device that is external to the integrated circuit device;
a reset circuit to generate a reset signal responsive to a first signal of the plurality of signals transmitted from the timer circuit, the reset signal to trigger a system reset of the integrated circuit device; and
an I/O circuit operably coupled to the I/O pins, the I/O circuit to operate the I/O pins in an electrically floating state responsive to a second signal of the plurality of signals transmitted by the timer circuit independent of the reset circuit.
2. The electrical system of claim 1 , wherein the second signal transmitted by the timer circuit comprises a safety signal.
3. The electrical system of claim 1 , wherein the integrated circuit device comprises an interrupt circuit, the interrupt circuit receiving a third signal transmitted from the timer circuit, wherein the interrupt circuit to trigger an interrupt of the CPU responsive to the received third signal independent of a state and a configuration of the interrupt circuit.
4. The electrical system of claim 3 , wherein the third signal comprises a non-maskable interrupt (NMI) signal.
5. The electrical system of claim 1 , wherein the timer circuit is external to the integrated circuit device.
6. The electrical system of claim 1 , wherein the first signal comprises a fault signal.
7. The electrical system of claim 3 , wherein the interrupt circuit of the integrated circuit device to receive a fourth signal from the timer circuit, the fourth signal to trigger an interrupt.
8. The electrical system of claim 5 , wherein the timer circuit to transmit a fifth signal of the plurality of signals to the integrated circuit device the fifth signal to trigger the system reset of the integrated circuit device independently of the reset circuit.
9. A processing circuit, comprising:
input/output (I/O) pins to conduct I/O signals between the processing circuit and a device that is external to the processing circuit;
an I/O circuit to selectively operate the I/O pins in an electrically floating state;
a reset circuit to, responsive to receipt of a fault signal, transmit a system reset signal to initiate a system reset of the processing circuit, the system reset to trigger the I/O circuit to operate the I/O pins in the electrically floating state; and
a timer circuit operably coupled to the I/O circuit and the reset circuit, the timer circuit to transmit a safety signal only to the I/O circuit, the safety signal to trigger the I/O circuit to operate the I/O pins in the electrically floating state independent of the system reset initiated via the reset circuit.
10. The processing circuit of claim 9 , comprising:
a central processing unit (CPU), the CPU operably coupled to the timer circuit; and
an interrupt circuit operably coupled to the timer circuit and to the CPU,
wherein the timer circuit to transmit a non-maskable interrupt signal to the interrupt circuit, the interrupt circuit to trigger an interrupt of the CPU, the interrupt initiable independently from a state and configuration of the interrupt circuit.
11. The processing circuit of claim 9 , comprising an interrupt circuit, and a central processing unit (CPU), the interrupt circuit and the CPU operably coupled to the timer circuit, wherein the timer circuit is to generate and transmit a reset signal to the CPU, the I/O circuit, and the interrupt circuit, wherein the reset signal to trigger a system reset of the processing circuit independently from the system reset signal of the reset circuit.
12. The processing circuit of claim 9 , wherein the timer circuit to transmit fault signal to the reset circuit responsive to a detection of a fault of the processing circuit.
13. A method of operating an integrated circuit device, the method comprising:
comparing a value indicated by a count register of a timer circuit to one or more thresholds, the one or more thresholds controlled by a central processing unit (CPU);
transmitting, by the timer circuit, a safety signal only to an input/output (I/O) circuit responsive to a detection that the value indicated by the count register is outside of one or more predetermined ranges of values defined by the one or more thresholds, the transmitting of the safety signal independent of either of a reset circuit and the CPU of the integrated circuit device; and
operating I/O pins of the integrated circuit device in an electrically floating state responsive to the safety signal.
14. The method of claim 13 , comprising transmitting, by the timer circuit, a non-maskable interrupt signal to an interrupt circuit of the integrated circuit device responsive to a determination that a detected fault merits an interrupt to operation of the CPU.
15. The method of claim 14 , comprising transmitting, by the timer circuit, a reset signal to trigger a system reset of the integrated circuit device independently from the reset circuit responsive to a determination that the detected fault merits the system reset.
16. The method of claim 15 , wherein the non-maskable interrupt signal is transmitted prior to transmitting the reset signal.
17. A method of operating a timer circuit, the method comprising:
detecting a fault in operation of an integrated circuit device:
asserting, responsive to a determination that the detected fault merits floating of input/output (I/O) pins, a first signal to trigger an I/O circuit of the integrated circuit device to operate I/O pins of the integrated circuit device in an electrically floating state independently of a central processing unit (CPU) or a reset circuit of the integrated circuit device;
asserting, responsive to a determination that the detected fault merits an interrupt of the integrated circuit device, a second signal to trigger a non-maskable interrupt of the integrated circuit device independently of a state and configuration of an interrupt circuit of the integrated circuit device; and
asserting, responsive to a determination that the detected fault merits a system reset, a third signal to trigger the system reset of the integrated circuit device independently of the reset circuit of the integrated circuit device.
18. The method of claim 17 , wherein detecting a fault comprises:
comparing a value indicated by a count register of the timer circuit to one or more thresholds; and
transmitting the third signal to place the integrated circuit device in a safe state.
19. The method of claim 18 , wherein the third signal is a system reset signal.
20. The method of claim 13 , comprising: implementing a functional safety mechanism to place the integrated circuit in a safe state responsive to a detected fault.