IP Library Granted Patent US 12,298,927
Granted Patent B2
US 12,298,927 · App. 16/946,500 · Granted May 13, 2025

Selectable input buffers of general purpose inputs and microcontrollers having the same

Inventors: Richard L. Hull (Puyallup, WA); Voltaire Ganchorre (Puyallup, WA)
Assignee: Microchip Technology Incorporated
G06F13/20G06F2213/40
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Quick Facts
Patent No.
US 12,298,927
App. No.
16/946,500
Granted
May 13, 2025
Kind
B2
Abstract

One or more embodiments relate, generally, to microcontroller input/output (I/O) and limiting or disabling static current draw at general purpose inputs, including during low power situations where a voltage input may be lower than a supply voltage. In some embodiments, a general purpose input may include selectable input buffers and logic that is configured to selectively enable an input buffer associated with a voltage domain substantially the same as an input voltage of the general purpose input, and selectively disable the other input buffers.

Claims (45)

1. A general purpose input of a microcontroller, the general purpose input comprising:

an input pin pad for operative coupling to a device external to a microcontroller;

a supply pin pad for operative coupling to a voltage supply to continuously power the general purpose input during multiple power states of the microcontroller; and

a circuitry to selectively disable static current draw at the general purpose input via enablement/disablement of two or more input buffers of the general purpose input, wherein the circuitry to selectively disable static current draw at least partially responsive to an input voltage at the input pin pad being lower than a supply voltage at the supply pin pad.

2. The general purpose input of claim 1 , wherein the voltage supply is an external voltage supply.

3. The general purpose input of claim 1 , further comprising

an on-board voltage regulator, the on-board voltage regulator comprising:

an input, the input operatively coupled to the supply pin pad; and

an output, the output operatively coupled to the circuitry arranged to selectively disable static current draw.

4. The general purpose input of claim 1 , wherein the circuitry arranged to selectively disable static current draw at the general purpose input is to disable static current draw responsive to control signals.

5. A microcontroller, comprising:

one or more general purpose inputs; and

a first input buffer of a first general purpose input of the one or more general purpose inputs, wherein an operative state of the first input buffer includes at least a first operative state and a second operative state, wherein the second operative state of the first input buffer is selectable, via an enable input of the first input buffer, to disable static current draw at the first general purpose input at least partially responsive to an input voltage at the first general purpose input being less than a supply voltage,

wherein a first operative state of the first input buffer is associated with an input of the first input buffer being enabled, and a second operative state of the first input buffer is associated with the input of the first input buffer being disabled.

6. The microcontroller of claim 5 , further comprising a second input buffer of the first general purpose input.

7. The microcontroller of claim 6 , further comprising:

a control logic of the first general purpose input, the control logic to provide control signals for enabling one of the first input buffer and the second input buffer.

8. The microcontroller of claim 7 , further comprising:

a control register operatively coupled to respective enable inputs of the first input buffer and the second input buffer.

9. The microcontroller of claim 6 , further comprising:

a first voltage shifter arranged on an enable input path of the second input buffer; and

a second voltage shifter arranged on an output path of the second input buffer.

10. The microcontroller of claim 9 , wherein the first voltage shifter is arranged to adjust a control signal to a voltage level of the second input buffer, and the second voltage shifter is arranged to adjust an output signal of the second input buffer to a logic voltage level.

11. The microcontroller of claim 6 , further comprising:

a voltage regulator of the first general purpose input, wherein an input of the voltage regulator is operatively coupled to a supply pin pad and an output of the voltage regulator is operatively coupled to the first input buffer.

12. The microcontroller of claim 11 , wherein the voltage regulator is arranged to receive the supply voltage and provide a regulated supply voltage responsive to the supply voltage.

13. The microcontroller of claim 12 , wherein the voltage regulator is to continuously generate and provide the regulated supply voltage during a lowest voltage mode.

14. The microcontroller of claim 12 , wherein the voltage regulator is to generate the regulated supply voltage within a device threshold voltage of a lowest specified input voltage.

15. The microcontroller of claim 12 , wherein the voltage regulator is an on-board voltage regulator.

16. A microcontroller, comprising:

a first supply pin pad;

a second supply pin pad; and

a general purpose input, the general purpose input comprising:

a first input buffer operatively coupled to the first supply pin pad;

a second input buffer operatively coupled to the second supply pin pad;

a third input buffer operatively coupled to a voltage regulator; and

a mapped control register, and

wherein enable inputs of the first, second, and third input buffers are operatively coupled to the mapped control register.

17. The microcontroller of claim 16 , wherein the general purpose input comprises an input pin pad, the input pin pad operatively coupled to the first input buffer, the second input buffer and the third input buffer.

18. A method, comprising:

receiving a supply voltage;

generating a regulated supply voltage responsive to the supply voltage;

providing the regulated supply voltage to a first input buffer of a first selectable input buffer;

providing the supply voltage to a second input buffer of the first selectable input buffer; and

while continuously providing the regulated supply voltage, selecting to enable the second input buffer and disable the first input buffer and thereby selectively disable static current draw at a first general purpose input at least partially responsive to an input voltage at the first general purpose input being less than the supply voltage.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 24, 2020
From: HULL, RICHARD L.; GANCHORRE, VOLTAIRE
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 053030/0465 →