IP Library Granted Patent US 11,476,208
Granted Patent B2
US 11,476,208 · App. 16/947,530 · Granted Oct 18, 2022

Grounding techniques for backside-biased semiconductor dice and related devices, systems and methods

Inventors: Behrooz Mehr (Chandler, AZ); Fernando Chen (Gilbert, AZ); Emmanuel de los Santos (Santa Clara, CA); Alex Kungo
Assignee: Microchip Technology Incorporated
H01L23/60H01L21/4853H01L23/3114H01L23/482H01L23/4825H01L23/49838H01L23/552H01L24/16H01L24/32H01L24/48H01L24/73H01L25/0657H01L25/50H01L23/3121H01L2224/0401H01L2224/04042H01L2224/05624H01L2224/05644H01L2224/05647H01L2224/16225H01L2224/16227H01L2224/2919H01L2224/2929H01L2224/32145H01L2224/32225H01L2224/32245H01L2224/48091H01L2224/48225H01L2224/48227H01L2224/4918H01L2224/49112H01L2224/73215H01L2224/73253H01L2224/73257H01L2224/73265H01L2224/83851H01L2225/0651H01L2225/06517H01L2225/06524H01L2225/06537H01L2225/06548H01L2225/06558H01L2225/06572H01L2225/06582H01L2924/00014H01L2924/1434H01L2924/19107H01L2924/3025
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,476,208
App. No.
16/947,530
Granted
Oct 18, 2022
Kind
B2
Abstract

Semiconductor devices may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Methods of making semiconductor devices may involve supporting a backside-biased semiconductor die supported above a substrate, a backside surface of the backside-biased semiconductor die being spaced from the substrate. The backside surface may be electrically connected to ground by wire bonds extending to the substrate. Systems may include a sensor device, a nontransitory memory device, and at least one semiconductor device operatively connected thereto. The at least one semiconductor device may include a substrate and a backside-biased semiconductor die supported above the substrate. A backside surface of the backside-biased semiconductor die may be electrically connected to ground by wire bonds extending to the substrate.

Claims (29)

1. A semiconductor device, comprising:

a substrate;

a backside-biased semiconductor die, comprising an active surface having integrated circuitry, a backside surface located on a side of the backside-biased semiconductor die opposite the active surface, an electrically insulating material interposed between the active surface and the backside surface, and semiconductor material located on opposite sides of the electrically insulating material and extending from the electrically insulating material to the active surface and the backside surface on the opposite sides of the electrically insulating material, wherein the electrically insulating material forms an electrical barrier insulating the semiconductor material proximate to the active surface from the semiconductor material proximate to the backside surface, a backside surface of the backside-biased semiconductor die being spaced from the substrate; and

a grounding interposer mechanically and electrically connected to the backside surface of the backside-biased semiconductor die by an electrically conductive material interposed between the backside surface of the backside-biased semiconductor die and the grounding interposer, the grounding interposer electrically connected to ground by one or more wire bonds extending to the substrate.

2. The semiconductor device of claim 1 , wherein the electrically conductive material interposed between the backside surface of the backside-biased semiconductor die and the grounding interposer comprises an adhesive material.

3. The semiconductor device of claim 1 , wherein the grounding interposer extends laterally beyond at least some side surfaces of the backside-biased semiconductor die.

4. The semiconductor device of claim 1 , wherein the backside-biased semiconductor die is in a flip-chip orientation, the active surface of the backside-biased semiconductor die facing the substrate.

5. The semiconductor device of claim 4 , further comprising another backside-biased semiconductor die located on a side of the grounding interposer opposite the substrate, a backside surface of the other backside-biased semiconductor die mechanically and electrically connected to the grounding interposer by another electrically conductive adhesive material.

6. The semiconductor device of claim 5 , wherein an active surface of the other backside-biased semiconductor die is electrically connected to at least one electrically conductive element of the substrate by at least one operative wire bond extending from the active surface of the other backside-biased semiconductor die to the at least one electrically conductive element.

7. The semiconductor device of claim 1 , wherein the grounding interposer comprises a plate of the electrically conductive material, a printed circuit board, a semiconductor chip, a redistribution layer, or a lead frame.

8. The semiconductor device of claim 1 , wherein the one or more wire bonds electrically connecting the grounding interposer to ground extend from an upper surface located on a side of the grounding interposer opposite the semiconductor die to the substrate.

9. The semiconductor device of claim 1 , wherein the one or more wire bonds electrically connecting the grounding interposer to ground extend from a lower surface of the grounding interposer facing semiconductor die to the substrate.

10. The semiconductor device of claim 9 , wherein the one or more wire bonds electrically connecting the grounding interposer to ground extend from one or more respective positions on the grounding interposer located laterally beyond lateral side surfaces of the semiconductor die.

11. The semiconductor device of claim 1 , wherein the grounding interposer comprises a semiconductor chip comprising electrically conductive vias extending between the opposite longitudinal sides thereof.

12. The semiconductor device of claim 11 , further comprising another backside-biased semiconductor die located on a side of the grounding interposer opposite the substrate, another backside surface of the other backside-biased semiconductor die electrically connected to the grounding interposer, the grounding interposer electrically connecting the backside surface of the semiconductor die and the other backside surface of the other semiconductor die to ground by the one or more wire bonds extending to the substrate.

13. The semiconductor device of claim 12 , further comprising one or more operative wire bonds extending from an active surface of the other semiconductor die to the substrate, each of the one or more operative wire bonds offset from each of the one or more wire bonds.

14. A method of making a semiconductor device, comprising:

supporting a backside-biased semiconductor die above a substrate, the backside-biased semiconductor die comprising an active surface having integrated circuitry, a backside surface located on a side of the backside-biased semiconductor die opposite the active surface, an electrically insulating material interposed between the active surface and the backside surface, and semiconductor material located on opposite sides of the electrically insulating material and extending from the electrically insulating material to the active surface and the backside surface on the opposite sides of the electrically insulating material wherein the electrically insulating material forms an electrical barrier insulating the semiconductor material proximate to the active surface from the semiconductor material proximate to the backside surface, the backside surface of the backside-biased semiconductor die being spaced from the substrate;

mechanically and electrically connecting a grounding interposer to the backside surface of the backside-biased semiconductor die utilizing an electrically conductive material interposed between the backside surface of the backside-biased semiconductor die and the grounding interposer; and

electrically connecting the backside surface to ground by wire bonds extending from the grounding interposer to the substrate.

15. The method of claim 14 , wherein mechanically and electrically connecting the grounding interposer to the backside surface of the backside-biased semiconductor die comprises mechanically and electrically connecting the grounding interposer to the backside surface utilizing an electrically conductive adhesive material.

16. The method of claim 15 , wherein supporting the backside-biased semiconductor die above the substrate comprises supporting the backside-biased semiconductor die above the substrate in a flip-chip orientation, the active surface of the backside-biased semiconductor die facing the substrate.

17. The method of claim 14 , wherein electrically connecting the backside surface to ground by the wire bonds comprises electrically connecting the backside surface to ground by wire bonds extending from an upper surface located on a side of the grounding interposer opposite the semiconductor die to the substrate.

18. The method of claim 14 , wherein electrically connecting the backside surface to ground by the wire bonds comprises electrically connecting the backside surface to ground by wire bonds extending from a lower surface of the grounding interposer facing the semiconductor die to the substrate.

19. The method of claim 14 , further comprising:

placing another backside-biased semiconductor die on a side of the grounding interposer opposite the substrate;

electrically connecting another backside surface of the other backside-biased semiconductor die to the grounding interposer; and

electrically connecting the backside surface of the semiconductor die and the other backside surface of the other semiconductor die to ground by the one or more wire bonds extending from the grounding interposer to the substrate.

20. The method of claim 19 , further comprising placing one or more operative wire bonds to extend from an active surface of the other backside-biased semiconductor die to the substrate, each of the one or more operative wire bonds offset from each of the one or more wire bonds.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 5, 2020
From: MEHR, BEHROOZ; CHEN, FERNANDO; DE LOS SANTOS, EMMANUEL
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 053414/0127 →