IP Library Granted Patent US 11,575,318
Granted Patent B2
US 11,575,318 · App. 16/947,785 · Granted Feb 7, 2023

Voltage converters with hysteretic control

Inventors: Alex Hsu (Hong Kong, HK); Paolo Nora (Belgioioso, IT)
Assignee: Microchip Technology Incorporated
H02M3/158H02M1/088H03K3/037H03K19/20H02M1/0048
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Quick Facts
Patent No.
US 11,575,318
App. No.
16/947,785
Granted
Feb 7, 2023
Kind
B2
Abstract

Various embodiments relate to a voltage converter including a control unit configured for operating in a hysteretic control mode. A control unit may be configured to receive a PWM signal, a duty cycle signal, at least one reference voltage, a factor of an output voltage of the voltage converter, and a factor of an input voltage of the voltage converter. The control unit may also be configured to compare the at least one reference voltage to the factor of the output voltage and the factor of the input voltage. Further, the control unit may be configured to generate a first control signal mirroring the PWM signal in response to at least one of: the factor of the input voltage being greater than the at least one reference voltage and the factor of the output voltage being greater than the at least one reference voltage. The control unit may also be configured to generate a second, different control signal including a low logic signal in response to the factor of the input voltage being less than or equal to the at least one reference voltage.

Claims (50)

1. A voltage converter, comprising:

a control unit including:

a first comparator configured to receive at least one reference voltage and a factor of an output voltage of the voltage converter, and generate a first signal;

a second comparator configured to receive the at least one reference voltage and a factor of an input voltage of the voltage converter, and generate a second signal;

a circuit configured to receive the first signal, the second signal, and a duty cycle signal, and generate a third signal; and

a logic gate configured to receive a first pulse-width modulation (PWM) signal and the third signal, and generate a control signal; and

a pulse generator configured to receive the control signal and generate the duty cycle signal based on the control signal.

2. The voltage converter of claim 1 , wherein the control signal mirrors the PWM signal in response to at least one of the factors of the input voltage being greater than the at least one reference voltage and the factor of the output voltage being greater than the at least one reference voltage.

3. The voltage converter of claim 1 , wherein the control signal comprises a static logic signal in response to the factor of the input voltage being less than or equal to the at least one reference voltage and the factor of the output voltage being less than or equal to the at least one reference voltage.

4. The voltage converter of claim 1 , wherein the control signal mirrors the PWM signal in response to the factor of the output voltage being greater than the at least one reference voltage.

5. The voltage converter of claim 1 , wherein the control signal mirrors the PWM signal during a pulse-frequency modulation (PFM) mode.

6. The voltage converter of claim 1 , wherein the control signal comprises a static logic signal during a bypass mode and a hysteretic control mode.

7. The voltage converter of claim 1 , wherein the at least one reference voltage comprises a first reference voltage and a second, different reference voltage, wherein the first comparator is configured to receive the first reference voltage and the second comparator is configured to receive the second, different reference voltage.

8. A voltage converter, comprising:

a control unit configured to:

receive a pulse-width modulation (PWM) signal, a duty cycle signal, at least one reference voltage, a factor of an output voltage of the voltage converter, and a factor of an input voltage of the voltage converter;

compare the at least one reference voltage to each of the factor of the output voltage and the factor of the input voltage;

generate a first control signal mirroring the PWM signal in response to at least one of the factors of the input voltage being greater than the at least one reference voltage and the factor of the output voltage being greater than the at least one reference voltage; and

generate a second, different control signal as a static logic signal in response to the factor of the input voltage being less than or equal to the at least one reference voltage.

9. The voltage converter of claim 8 , wherein the control unit comprises:

a first comparator configured to receive the at least one reference voltage and the factor of the output voltage;

a second comparator configured to receive the at least one reference voltage and the factor of the input voltage;

a first inverter having an input configured to receive an output of the first comparator;

a flip-flop having a first input configured to receive an output of the second comparator, a second input configured to receive an output of the first inverter, and a third input configured to receive the duty cycle signal;

a second inverter configured to receive an output of the flip-flop; and

an AND gate having a first input configured to receive the PWM signal and a second input configured to receive an output of the second inverter.

10. The voltage converter of claim 8 , wherein the control unit comprises:

a first comparator configured to receive the at least one reference voltage and the factor of the output voltage and generate a first signal;

a first inverter configured to receive the first signal and generate a second signal;

a second comparator configured to receive the at least one reference voltage and the factor of the input voltage and generate a third signal;

a flip-flop configured to receive the second signal, the third signal, and the duty cycle signal, and generate a fourth signal;

a second inverter configured to receive the fourth signal and generate a fifth signal; and

an AND gate configured to receive the PWM signal and the fifth signal and generate a control signal.

11. The voltage converter of claim 8 , further comprising a pulse generator configured to generate the duty cycle signal based on one of the first control signal and the second, different control signal.

12. The voltage converter of claim 11 , wherein the pulse generator includes:

a first NAND gate configured to receive the duty cycle signal and a third control signal;

a second NAND gate configured to receive an output of the first NAND gate and one of the first control signal and the second, different control signal; and

a second flip-flop configured to receive an output of the second NAND gate and generate the duty cycle signal.

13. The voltage converter of claim 8 , wherein the at least one reference voltage comprises a first reference voltage and a second reference voltage.

14. The voltage converter of claim 13 , wherein the control unit is configured to compare the first reference voltage to the factor of the output voltage and the second reference voltage to the factor of the input voltage.

15. A method of operating a voltage converter, comprising:

receiving, at a control unit of a voltage converter, a pulse-width modulation (PWM) signal, a duty cycle signal, at least one reference voltage, a factor of an output voltage of the voltage converter, and a factor of an input voltage of the voltage converter;

comparing, via the control unit, the at least one reference voltage to each of the factor of the output voltage and the factor of the input voltage;

generating, via the control unit, a first control signal mirroring the PWM signal in response to at least one of the factors of the input voltage being greater than the at least one reference voltage and the factor of the output voltage being greater than the at least one reference voltage; and

generating, via the control unit, a second, different control signal as a static logic signal in response to the factor of the input voltage being less than or equal to the at least one reference voltage and the factor of the output voltage being less than or equal to the at least one reference voltage.

16. The method of claim 15 , further comprising generating the duty cycle signal based on one of the first control signal and the second, different control signal.

17. The method of claim 15 , further comprising conveying one of the first control signal and the second, different control signal to a pulse generator.

18. The method of claim 15 , further comprising enabling the control unit based on a signal received via a bus.

19. The method of claim 15 , wherein generating the first control signal comprises: receiving the PWM signal and a logic high signal at an AND gate; and outputting the first control signal from the AND gate.

20. The method of claim 15 , wherein generating the second, different control signal comprises: receiving the PWM signal and a logic low signal at an AND gate; and outputting the second, different control signal from the AND gate.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059357/0823 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0335 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059264/0384 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 058214/0380 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0625 →
GRANT OF SECURITY INTEREST IN PATENT RIGHTS Recorded Nov 19, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 058214/0238 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2020
From: HSU, ALEX; NORA, PAOLO
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 053514/0833 →
Priority Claims (1)
CN 201910870625.6 · Sep 16, 2019 · national
Continuity (1)
Related Publication 20210083579A1 · Mar 18, 2021