Autonomous transmit error detection of serial communication link receiver-transmitter and microcontroller system peripherals implementing the same
A serial communication link receiver-transmitter with autonomous transmission error detection is described, and a communication peripherals including the same. Transmit data at a transmitter and transmitted data output by the transmitter and received by the receiver are observed by an error detector configured to generate an error indication in response to difference between the transmit data and corresponding observed transmit data of a transmitted data frame. If a difference is detected a transmit error indicator is asserted.
1. An apparatus, comprising:
a transmitter and a receiver for data transmission and data reception, respectively, at a same side of a serial communication link; and
an error detector operatively coupled to the transmitter and receiver, the error detector to provide, during a normal data transmission mode of the transmitter and a normal data reception mode of the receiver, a transmit error indication responsive to a difference between transmit data received at the transmitter and transmitted data output by the transmitter.
2. The apparatus of claim 1 , wherein the error detector comprises:
a transmit error indicator;
a comparison register; and
an error detection logic comprising:
a first input operatively coupled to the comparison register;
a second input operatively coupled to a memory of the receiver; and
an output operatively coupled to the transmit error indicator.
3. The apparatus of claim 2 , wherein an enable input of the error detection logic is coupled to a reception complete indicator of the receiver.
4. The apparatus of claim 1 , wherein the transmitter comprises a data buffer operatively coupled to the error detector.
5. The apparatus of claim 4 , wherein the error detector is arranged to observe transmit data provided to a transmit shift register and to store an observed transmit data.
6. The apparatus of claim 1 , wherein an output of the transmitter is operatively coupled to an output pad and operatively coupled to an input of the receiver.
7. The apparatus of claim 6 , wherein the receiver is to receive an observed transmitted data frame and obtain an observed transmitted data of the observed transmitted data frame.
8. The apparatus of claim 1 , comprising: a selection circuitry to alternately couple and de-couple an input of the receiver to an output of the transmitter responsive to a selection signal, the selection signal generated in response to enablement/de-enablement of the error detector.
9. The apparatus of claim 1 , comprising: a selection circuitry to alternately couple and de-couple an input of the receiver to an input pad responsive to a selection signal, the selection signal generated in response to enablement/de-enablement of the error detector.
10. A method the comprising:
during a normal data transmission mode of a transmitter and a normal data reception mode of a receiver, respectively of a same side of a serial communication link, serially outputting a transmitted data frame including transmit data; and
asserting an error indicator responsive to determining that an observed transmitted data is different than an observed transmit data.
11. The method claim 10 , comprising:
observing transmit data at a transmitter of a serial communication link receiver-transmitter.
12. The method of claim 10 , comprising: observing the transmitted data frame serially output by a transmitter.
13. The method of claim 10 , comprising:
receiving an observed transmitted data at a receiver of a serial communication link receiver-transmitter according to a data reception transaction process of a receiver.
14. The method of claim 13 , comprising:
upon completing the normal data reception transaction process of the observed transmitted data, comparing the observed transmitted data of the observed transmitted data frame to the observed transmit data.
15. The method of claim 10 , comprising: comparing an observed transmitted data and the observed transmit data; and determining that the observed transmitted data is different than the observed transmit data responsive to the comparing.
16. A system, comprising:
a processor; and
a memory storage having thereon machine-executable code adapted to permanently configure logic circuitry of the processor to:
observe a transmit data received for transmission by a transmitter of a serial communication link;
during a normal data transmission mode of a transmitter and a normal data reception mode of a receiver, respectively of a same side of a serial communication link, serially output a transmit data frame including transmitted data;
observe the transmitted data of the transmit data frame; and
assert an error indicator responsive to determining that the observed transmitted data is different than an observed transmit data.
17. The system of claim 16 , wherein the machine-executable code includes code adapted to permanently configure logic circuitry of the processor to:
observe transmit data at a transmitter of a serial communication link receiver-transmitter.
18. The system of claim 17 , wherein the machine-executable code includes code adapted to permanently configure logic circuitry of the processor to: observe a transmitted data frame serially output by the transmitter.
19. The system of claim 16 , wherein the machine-executable code includes code adapted to permanently configure logic circuitry of the processor to:
receive the observed transmitted data of the transmit data frame at a receiver of a serial communication link receiver-transmitter according to a data reception transaction process of the receiver.
20. The system of claim 19 , wherein the machine-executable code includes code adapted to permanently configure logic circuitry of the processor to:
upon completing the data reception transaction process of the observed transmitted data frame,
compare the observed transmitted data of the transmitted data frame to the observed transmit data.
21. The system of claim 19 , wherein the machine-executable code includes code adapted to permanently configure logic circuitry of the processor to:
compare the observed transmitted data and the observed transmit data; and determining that the observed transmitted data is different than the observed transmit data responsive to the comparing.