Analog neural memory array in artificial neural network with substantially constant array source impedance with adaptive weight mapping and distributed power
Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.
1. An analog neural memory system comprising:
an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a different bit line in a plurality of bitlines, and each column of cells in a second plurality of columns of cells is connected to a different dummy bit line in a plurality of dummy bitlines;
a set of dummy bit line switches arranged on a first end of the array, each of the set of dummy bit line switches coupled to one of the dummy bit lines in the plurality of dummy bitlines;
a set of bit line switches arranged on a second end of the array opposite the first end of the array, each of the set of bit line switches coupled to one of the bit lines in the plurality of bit lines; and
a summer for summing outputs from one or more bit lines, wherein the summer is adjustable based on a variable resistor or a variable capacitor;
wherein during a read operation of a selected cell in the first plurality of columns of cells, current passes through a path formed in a bit line switch in the set of bit line switches coupled to the bit line connected to the selected cell in the first plurality of column of cells, the selected cell, a dummy bit line, and a dummy bit line switch in the set of dummy bit line switches into the summer.
2. The system of claim 1 , wherein each dummy bit line switch in the set of dummy bit line switches is configured to pull the coupled dummy bit line to ground.
3. The system of claim 2 , wherein array bit line interconnect impedance remains substantially constant when cells attached to the plurality of bit lines are selected for a read operation.
4. The system of claim 1 , wherein two or more of the dummy bit line switches in the first set of dummy bit line switches are connected to a common ground.
5. The system of claim 1 , wherein two or more of the bit lines are coupled to one another.
6. The system of claim 1 , wherein array bit line interconnect impedance remains substantially constant when cells attached to the plurality of bit lines are selected for a read operation.
7. The system of claim 1 , wherein the set of bit line switches couples to one or more of a sensing circuit, a summer, or an analog-to-digital converter circuit.
8. The system of claim 1 , wherein the non-volatile memory cells in the array are split gate flash memory cells.
9. The system of claim 1 , wherein the non-volatile memory cells in the array are stacked gate flash memory cells.
10. The system of claim 1 , wherein the summer is adjustable based on a variable resistor.
11. The system of claim 1 , wherein the summer is adjustable based on a variable capacitor.
12. The system of claim 1 , further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.
13. The system of claim 12 , wherein the analog-to-digital converter comprises a successive approximation register.
14. The system of claim 13 , wherein the analog-to-digital converter is a pipelined analog-to-digital converter.
15. The system of claim 1 , further comprising:
a source line coupled to a source line terminal of a row of non-volatile memory cells; and
a source line transistor configured to pull the source line to ground.
16. The system of claim 15 , wherein array interconnect impedance remains substantially constant when cells attached to the bit lines are selected for operation.
17. The system of claim 15 , wherein the bit line switches couples to one or more of a sensing circuit, a summer, or an analog-to-digital converter circuit.
18. The system of claim 15 , wherein two or more of the dummy bit line switches in the set of dummy bit line switches are connected to a common ground.
19. An analog neural memory system comprising:
a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a different bit line in a plurality of bitlines, and each column of cells in a second plurality of columns of cells is connected to a different dummy bit line in a plurality of dummy bitlines;
a second array of non-volatile memory cells, the cells in the second array arranged in rows and columns, wherein a second plurality of columns of cells in the second array is connected to a different bit line in the plurality of bit lines and a second plurality of columns of cells in the second array is connected to a different dummy bit line in a plurality of dummy bitlines; and
a set of multiplexors coupled to the first array and the second array and coupled to ground;
wherein array interconnect impedance of the first array and the second array remain substantially constant when cells attached to the bit lines are selected for operation.
20. The system of claim 19 , wherein the non-volatile memory cells in the first array and the second array are split gate flash memory cells.
21. The system of claim 19 , wherein the non-volatile memory cells in the first array and the second array are stacked gate flash memory cells.
22. The system of claim 19 , further comprising a summer for summing outputs from one or more bit lines.
23. The system of claim 22 , wherein the summer is adjustable based on a variable resistor.
24. The system of claim 22 , wherein the summer is adjustable based on a variable capacitor.
25. The system of claim 22 , further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.
26. The system of claim 25 , wherein the analog-to-digital converter comprises a successive approximation register.
27. The system of claim 26 , wherein the analog-to-digital converter is a pipelined analog-to-digital converter.
28. A method of operating an analog neural memory system comprising a first array comprising non-volatile memory cells arranged in rows and columns, a second array comprising non-volatile memory cells arranged in rows and columns, column multiplexors, local bit lines, and global bit lines, the method comprising:
selecting, by the column multiplexors, a local bit line of the first array or a local bit line of the second array, and coupling the selected bit line to a global bit line; and
multiplexing the global bit line with a second global bit line adjacent to the global bit line.
29. The method of claim 28 , further comprising:
summing outputs from one or more global bit lines.
30. A method of operating an analog neural memory system comprising an array of non-volatile memory cells, the method comprising:
receiving, by a first n-bit analog-to-digital converter, a first output from the array;
receiving, by a second n-bit analog-to-digital converter, a second output from the array;
combining the first n-bit analog-to-digital converter with the second n-bit analog-to-digital converter to form a third analog-to-digital converter that generates a third output based on the first output and the second output, wherein the third output has a precision greater than n bits.
31. The method of claim 30 , wherein the first analog-to-digital converter is a serial analog-to-digital converter and the second analog-to-digital converter is a serial analog-to-digital converter.
32. The method of claim 30 , wherein the first analog-to-digital converter is a successive approximation converter and the second analog-to-digital converter is a successive approximation converter.
33. An analog neural memory system comprising:
an array of non-volatile memory cells, wherein the cells are arranged in rows and columns, wherein each column of cells in a first plurality of columns of cells is connected to a bit line in a plurality of bitlines, and weights of a neural network are distributed among the bitlines to maintain voltage drop or power consumption at a substantially equal level among the bitlines.
34. The system of claim 33 , wherein the non-volatile memory cells in the array are split gate flash memory cells.
35. The system of claim 33 , wherein the non-volatile memory cells in the array are stacked gate flash memory cells.
36. The system of claim 33 , further comprising a summer for summing outputs from one or more bit lines.
37. The system of claim 36 , wherein the summer is adjustable based on a variable resistor.
38. The system of claim 36 , wherein the summer is adjustable based on a variable capacitor.
39. The system of claim 36 , further comprising an analog-to-digital converter for converting an output of the summer into a digital signal.
40. The system of claim 39 , wherein the analog-to-digital converter comprises a successive approximation register.
41. The system of claim 40 , wherein the analog-to-digital converter is a pipelined analog-to-digital converter.