Semiconductor device having a pad proximate to a step structure section of an array chip

1. A semiconductor memory device comprising:

an array chip including

a first substrate,

a stacked body provided below the first substrate and including a plurality of electrode layers stacked via an insulating layer in a first direction, end portions, in a second direction crossing the first direction, of the plurality of electrode layers being formed in a step shape in a step structure section,

a semiconductor body extending in the first direction in the stacked body,

a charge storage film provided between the semiconductor body and the plurality of electrode layers,

a bit line provided below the stacked body and connected to an end portion of the semiconductor body,

a memory-side interconnection layer provided below the bit line and electrically connected to the bit line, and

a first pad provided in a first section closer to an end of the array chip than the step structure section in the second direction,

a circuit chip provided below the array chip and stuck to the array chip, the circuit chip including

a second substrate,

a transistor provided on the second substrate, and

a circuit-side interconnection layer provided above the transistor and electrically connected to the transistor, the circuit-side interconnection layer provided below the memory-side interconnection layer of the array chip; and

a bonding metal provided between the memory-side interconnection layer and the circuit-side interconnection layer in the first direction, and electrically connected to the memory-side interconnection layer and the circuit-side interconnection layer; wherein

the first pad is electrically connected to the transistor via the circuit-side interconnection layer and the memory-side interconnection layer.

2. The device according to claim 1 , wherein the array chip includes a source line connected to another end portion of the semiconductor body.

3. The device according to claim 2 , wherein the first pad is provided in a same layer as the source line and formed of a same material as the source line.

4. The device according to claim 1 , wherein the memory-side interconnection layer includes word interconnection layers electrically connected to the electrode layers.

5. The device according to claim 4 , wherein the first pad is provided in a same layer as the word interconnection layers and formed of a same material as the word interconnection layers.

6. The device according to claim 4 , wherein the bonding metal includes a plurality of word-line lead-out sections electrically connected to the word interconnection layers.

7. The device according to claim 6 , wherein the first pad is provided in a region overlapping the word-line lead-out sections in the first direction.

8. The device according to claim 6 , wherein the first pad is provided in a region overlapping the word-line lead-out sections in the first direction.

9. The device according to claim 1 , further comprising an insulating film provided around the bonding metal.

10. The device according to claim 1 , wherein

the step structure section is provided at an end of a memory cell array region where the semiconductor body and the charge storage film are disposed, and

the memory-side interconnection layer includes word interconnection layers connected to the electrode layers formed in the step shape.

11. The device according to claim 10 , wherein the first pad is formed in a region further on an outer side than the memory cell array region.