Semiconductor memory device including integrated control circuit and solid-state drive controller
According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
1. A semiconductor memory device comprising:
a semiconductor substrate;
a control circuit provided on the semiconductor substrate;
a solid state drive controller provided on the semiconductor substrate;
a first interconnection layer provided above the control circuit and the solid state drive controller;
a second interconnection layer provided above the first interconnection layer and including a plurality of bit lines; and
a three-dimensionally disposed plurality of memory cells above the plurality of bit lines and electrically connected to the control circuit through the first interconnection layer and the second interconnection layer, wherein
the control circuit is electrically connected to the solid state drive controller through the first interconnection layer,
a plurality of transistors consisting of the solid state drive controller are located on at least two areas of the semiconductor substrate, and
the control circuit includes at least one transistor disposed on an area between two areas among the at least two areas of the semiconductor substrate.
2. The device according to claim 1 , wherein the control circuit is electrically connected to the second interconnection layer through the first interconnection layer.
3. The device according to claim 1 , wherein the three-dimensionally disposed memory cells includes a plurality of semiconductor bodies, a plurality of electrode layers facing to the plurality of semiconductor bodies, a charge storage film provided between one of the plurality of semiconductor bodies and the plurality of electrode layers, and one of the plurality of bit lines electrically connected to an end portion of one of the plurality of semiconductor bodies.
4. The device according to claim 3 , wherein the bit lines are provided between the electrode layers and the second interconnection layer.
5. The device according to claim 3 , wherein the control circuit includes a row decoder controlling potentials of the electrode layers, and a sense amplifier sensing and amplifying potentials of the bit lines.
6. The device according to claim 3 , wherein
the electrode layers are formed in a step shape at an end of a memory cell array region where the memory cells are disposed, and
the second interconnection layer includes word interconnection layers connected to the electrode layers formed in the step shape.
7. The device according to claim 3 , further comprising:
a first select gate layer provided between a lower most layer of the electrode layers and the bit lines, and
a second select gate layer provided above an upper most layer of the electrode layers.
8. The device according to claim 3 , further comprising:
a first select gate layer provided between a lower most layer of the electrode layers and the bit lines, the first select gate layer electrically connected to the second interconnection layer, and
a second select gate layer provided above an upper most layer of the electrode layers, the second select gate layer electrically connected to the second interconnection layer.
9. The device according to claim 3 , wherein the semiconductor bodies extend in a stacking direction of a stacked body including the electrode layers stacked via an insulating layer.
10. The device according to claim 3 , further comprising a source line connected to other end portions of the semiconductor bodies.
11. The device according to claim 1 , wherein the second interconnection layer is provided between the bit lines and the first interconnection layer.
12. The device according to claim 1 , wherein the control circuit includes MOSFETs formed on the semiconductor substrate.
13. The device according to claim 1 , wherein the solid state drive controller includes MOSFETs formed on the semiconductor substrate.
14. The device according to claim 1 , further comprising a pad provided in a same layer as the first interconnection layer and formed of a same material as the second interconnection layer.
15. The device according to claim 14 , further comprising an external connection electrode extending to an upper surface of the pad.