Minimizing shorting between FinFET epitaxial regions
The present invention relates generally to semiconductors, and more particularly, to a structure and method of minimizing shorting between epitaxial regions in small pitch fin field effect transistors (FinFETs). In an embodiment, a dielectric region may be formed in a middle portion of a gate structure. The gate structure be formed using a gate replacement process, and may cover a middle portion of a first fin group, a middle portion of a second fin group and an intermediate region of the substrate between the first fin group and the second fin group. The dielectric region may be surrounded by the gate structure in the intermediate region. The gate structure and the dielectric region may physically separate epitaxial regions formed on the first fin group and the second fin group from one another.
1. A method comprising:
forming an opening in a dummy gate layer between a first fin group and a second fin group, wherein the opening extends through the dummy gate layer;
forming a dielectric region in the opening;
forming a first dummy gate and a second dummy gate by patterning the dummy gate layer, wherein (i) the first dummy gate covers a portion of the first fin group and (ii) the second dummy gate covers a portion of the second fin group, and wherein the dielectric region separates the first dummy gate from the second dummy gate;
forming a spacer on (i) an outer surface the first dummy gate, (ii) an outer surface of the second dummy gate, and (iii) an outer surface of the dielectric region; and
replacing (i) the first dummy gate with a first replacement gate and (ii) the second dummy gate with a second replacement gate.
2. The method of claim 1 , wherein replacing (i) the first dummy gate with the first replacement gate and (ii) the second dummy gate with the second replacement gate comprises removing the first dummy gate and the second dummy gate selective to the dielectric region and the spacer.
3. The method of claim 1 , wherein forming the dielectric region in the opening comprises:
depositing a dielectric material in the opening; and
planarizing the dielectric material.
4. The method of claim 3 , wherein the dielectric material is planarized to have an upper surface substantially flush with an upper surface of the dummy gate layer.
5. The method of claim 1 , further comprising:
forming a first epitaxial region on an exposed portion of the first fin group; and
forming a second epitaxial region on an exposed portion of the second fin group, wherein the dielectric region isolates the first epitaxial region from the second epitaxial region.
6. The method of claim 1 , wherein at least one of (i) the first fin group comprises fins comprising silicon germanium or (ii) the second fin group comprises fins comprising silicon germanium.
7. The method of claim 1 , wherein a width of both the first replacement gate and the second replacement gate is less than a width of the dielectric region.
8. The method of claim 1 , wherein both the first replacement gate and the second replacement gate comprise tungsten, aluminum, titanium, or alloys thereof.
9. The method of claim 1 , wherein the first replacement gate and the second replacement gate are in direct contact with the dielectric region.
10. A method comprising:
forming an opening in a dummy gate layer between a first fin group and a second fin group, wherein the opening extends through the dummy gate layer;
forming a dielectric region in the opening;
forming a first dummy gate and a second dummy gate by patterning the dummy gate layer, wherein (i) the first dummy gate covers a portion of the first fin group and (ii) the second dummy gate covers a portion of the second fin group, and wherein the dielectric region separates the first dummy gate from the second dummy gate; and
replacing (i) the first dummy gate with a first replacement gate and (ii) the second dummy gate with a second replacement gate.
11. The method of claim 10 , wherein forming the dielectric region in the opening comprises:
depositing a dielectric material in the opening; and
planarizing the dielectric material.
12. The method of claim 11 , wherein the dielectric material is planarized to have an upper surface substantially flush with an upper surface of the dummy gate layer.
13. The method of claim 10 , wherein the dummy gate layer comprises polysilicon.
14. The method of claim 10 , wherein both the first replacement gate and the second replacement gate comprise tungsten, aluminum, titanium, or alloys thereof.
15. The method of claim 10 , wherein both the first replacement gate and the second replacement gate comprise polysilicon, copper, gold, ruthenium, platinum, or alloys thereof.
16. The method of claim 10 , further comprising:
forming a spacer on (i) exposed vertical sidewalls of the first dummy gate, (ii) exposed vertical sidewalls of the second dummy gate, and (iii) exposed vertical sidewalls of the dielectric region.
17. The method of claim 10 , further comprising:
forming a first epitaxial region on an exposed portion of the first fin group; and
forming a second epitaxial region on an exposed portion of the second fin group, wherein the dielectric region isolates the first epitaxial region from the second epitaxial region.
18. The method of claim 10 , wherein at least one of the first fin group or the second fin group comprises fins comprising silicon germanium.
19. The method of claim 10 , wherein a width of both the first replacement gate and the second replacement gate is less than a width of the dielectric region.
20. The method of claim 10 , wherein the first replacement gate and the second replacement gate are in direct contact with the dielectric region.