Semiconductor device and method for manufacturing same
According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
1. A semiconductor device, comprising:
a first semiconductor layer;
a stacked body provided above the first semiconductor layer, the stacked body including a plurality of electrode layers stacked in a first direction; and
a columnar portion including a second semiconductor layer and a charge storage film, wherein
the second semiconductor layer extends through the stacked body and reaches the first semiconductor layer in the first direction and includes a side wall portion in contact with the first semiconductor layer,
the charge storage film includes a first portion between the plurality of electrode layers and the second semiconductor layer, and a second portion between the second semiconductor layer and the first semiconductor layer,
the first portion and the second portion are completely separated from each other in the first direction by the first semiconductor layer, and
the side wall portion of the second semiconductor layer is not covered with the charge storage film,
an impurity concentration of the side wall portion of the second semiconductor layer is higher than an impurity concentration of a portion of the second semiconductor layer opposing the stacked body.
2. The semiconductor device according to claim 1 , wherein the first semiconductor layer includes an impurity.
3. The semiconductor device according to claim 1 , further comprising a gate layer provided between the first semiconductor layer and the stacked body, the gate layer being thicker than a thickness of one layer of the plurality of electrode layers.
4. The semiconductor device according to claim 3 , wherein a distance between the side wall portion and a portion of the second semiconductor layer opposing the gate layer is less than a thickness of the gate layer.
5. The semiconductor device according to claim 3 , wherein an impurity concentration of a first portion of the second semiconductor layer opposing the gate layer is higher than an impurity concentration of a second portion of the second semiconductor layer opposing the stacked body.
6. The semiconductor device according to claim 3 , wherein
the plurality of electrode layers include:
at least one first electrode layers functioning as at least one selection gates and each being thinner than the gate layer;
at least one second electrode layers functioning as at least one selection gates, provided between the at least one first electrode layers and the gate layer, and each being thinner than the gate layer; and
a plurality of third electrode layers functioning as a plurality of cell Rates, provided between the at least one first electrode layers and the at least one second electrode layers, and each being thinner than the gate layer.
7. The semiconductor device according to claim 3 , wherein the gate layer is a silicon layer including phosphorus.
8. The semiconductor device according to claim 1 , wherein the first semiconductor layer is a silicon layer including phosphorus.
9. The semiconductor device according to claim 3 , further comprising a layer including a metal, the first semiconductor layer being provided between the gate layer and the layer including the metal.
10. The semiconductor device according to claim 1 , wherein the charge storage film is continuous in the first direction between the stacked body and the second semiconductor layer.
11. The semiconductor device according to claim 3 , wherein the charge storage film is provided between the gate layer and the second semiconductor layer.
12. The semiconductor device according to claim 3 , wherein a portion of the second semiconductor layer opposing the gate layer includes an impurity so that the gate layer generates gate induced leakage in an erase operation.
13. The semiconductor device according to claim 1 , wherein an air gap is formed in the first semiconductor layer.
14. The semiconductor device according to claim 1 , further comprising a substrate, the first semiconductor layer being provided between the substrate and the stacked body layer, the first semiconductor layer contacting the substrate.
15. The semiconductor device according to claim 14 , wherein
the substrate includes
an n-type semiconductor region contacting the first semiconductor layer, and
a p-type semiconductor region, the n-type semiconductor region and the p-type semiconductor region forming a p-n junction.
16. The semiconductor device according to claim 14 , wherein the second semiconductor layer pierces the first semiconductor layer, and a lower end portion of the second semiconductor layer reaches the substrate.