Granted Patent B2

US 12,696,492 · App. 17/238,553 · Granted Jul 28, 2026

Inventors: Brian Mattis (Austin, TX); Ke Liu (Austin, TX); Taran Huffman (Austin, TX); Bryan Woo (Goleta, CA)

Assignee: ORCA Computing Limited

H10D30/68G02B6/12007G02B6/1228H10B41/30G02B2006/12061G02B6/2935

Abstract

Claims (45)

1 . A semiconductor device comprising:

a source electrode;

a control electrode;

an insulator layer; and

a floating gate separated from the source electrode and the control electrode by the insulator layer, the floating gate optically coupled to and electrically isolated from a photonic circuit and configured to operate as a waveguide of the photonic circuit, the floating gate operable to accumulate electrical charge across the insulator layer via quantum tunneling.

2 . The semiconductor device of claim 1 , wherein the insulator layer comprises a first portion separating the source electrode from the floating gate and a second portion separating the control electrode from the floating gate.

3 . The semiconductor device of claim 2 , wherein the second portion of the insulator layer is an oxide-nitride-oxide dielectric layer.

4 . The semiconductor device of claim 1 , wherein the floating gate comprises a silicon optical waveguide.

5 . The semiconductor device of claim 1 , further comprising a drain electrode separated from the floating gate by the insulator layer.

6 . The semiconductor device of claim 1 , wherein the photonic circuit comprises an interferometer or a ring resonator.

7 . The semiconductor device of claim 6 , wherein the interferometer is a Mach-Zehnder interferometer.

8 . The semiconductor device of claim 6 , wherein the interferometer comprises:

a first arm; and

a second arm including the floating gate.

9 . A semiconductor device comprising:

a conductive element;

a layered dielectric disposed below the conductive element, the layered dielectric comprising:

a first silicon oxide layer formed to interface the conductive element;

a silicon nitride layer formed to interface the first silicon oxide layer; and

a second silicon oxide layer formed to interface the silicon nitride layer;

a silicon waveguide formed to interface the second silicon oxide layer of the layered dielectric, the silicon waveguide:

optically coupled to a photonic circuit; and

conductively decoupled from the conductive element, thereby operating as a floating gate; wherein:

in response to a voltage applied to the conductive element, the silicon waveguide accumulates charge by quantum tunneling, the accumulated charge effecting a change in a refractive index of the silicon waveguide.

10 . The semiconductor device of claim 9 , wherein the silicon waveguide is a first waveguide and the silicon nitride layer is a second waveguide.

11 . The semiconductor device of claim 9 , wherein the silicon waveguide is the floating gate of a memory cell of which the conductive element is a control gate.

12 . The semiconductor device of claim 11 , wherein the memory cell comprises a source gate separated from the silicon waveguide by an insulator layer, the source gate configured to supply the charge accumulated by the silicon waveguide in response to the voltage applied to the control gate.

13 . The semiconductor device of claim 9 , wherein:

the photonic circuit comprises an interferometer defining a first optical path and a second optical path; and

the silicon waveguide is optically coupled into the first optical path.

14 . The semiconductor device of claim 9 , wherein the silicon waveguide comprises a first end defining a first adiabatic taper and a second end defining a second adiabatic taper.

15 . A nonvolatile semiconductor memory comprising:

an array of memory cells, each memory cell comprising:

a source gate;

a control gate;

an optical input;

an optical output;

a first waveguide defining a first optical path optically coupling the optical input to the optical output; and

a second waveguide defining a second optical path optically coupling the optical input to the optical output, the second waveguide conductively decoupled from the source gate and the control gate, and configured to accumulate and retain, via quantum tunneling, electrical charge supplied by the source gate in response to a voltage applied to the control gate such that the second optical path exhibits a different index of refraction from the first optical path.

16 . The nonvolatile semiconductor memory of claim 15 , wherein:

a subset of the array of memory cells are conductively coupled by a word line; and

each memory cell of the subset of the array are conductively coupled to a respective one bit line.

17 . The nonvolatile semiconductor memory of claim 15 , further comprising a light source optically coupled to a respective optical input of at least one memory cell of the array of memory cells.

18 . The nonvolatile semiconductor memory of claim 15 , wherein the first waveguide and the second waveguide define a Mach-Zehnder interferometer.

19 . The nonvolatile semiconductor memory of claim 15 , wherein at least one memory cell of the array of memory cells is a portion of a configurable logic block of a field programmable gate array.

Assignments (3)

Continuity (2)

References Cited (275)