IP Library › Granted Patent US 12,396,155
Granted Patent B2
US 12,396,155 · App. 17/351,301 · Granted Aug 19, 2025

Backend memory with air gaps in upper metal layers

Inventors: Abhishek A. Sharma (Hillsboro, OR); Albert B. Chen (Portland, OR); Wilfred Gomes (Portland, OR); Fatih Hamzaoglu (Portland, OR); Travis W. Lajoie (Forest Grove, OR); Van H. Le (Beaverton, OR); Alekhya Nimmagadda (Hillsboro, OR); Miriam R. Reshotko (Portland, OR); Hui Jae Yoo (Hillsboro, OR)
Assignee: Intel Corporation
H10B12/30H01L23/5283H10B12/02H10D62/115
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Quick Facts
Patent No.
US 12,396,155
App. No.
17/351,301
Granted
Aug 19, 2025
Kind
B2
Abstract

An example IC device includes a frontend layer and a backend layer with a metallization stack. The metallization stack includes a backend memory layer with a plurality of memory cells with backend transistors, and a layer with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps between adjacent ones of the plurality of interconnects. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory.

Claims (77)

1. An integrated circuit (IC) device, comprising:

a frontend layer, comprising a plurality of frontend devices; and

a backend layer, comprising a layer that includes a plurality of backend memory cells and a layer that includes a plurality of conductive interconnects coupled to one or more of the plurality of backend memory cells and the plurality of frontend devices,

wherein:

at least some pairs of adjacent conductive interconnects of the plurality of conductive interconnects have an air gap between the adjacent conductive interconnects, and

the layer that includes the plurality of backend memory cells is between the frontend layer and the layer that includes the plurality of conductive interconnects.

2. The IC device according to claim 1 , wherein:

a sealing material is at least partially at a first sidewall, a bottom, and a second sidewall of the air gap,

an individual pair of the adjacent conductive interconnects with the air gap in between includes a first conductive interconnect and a second conductive interconnect,

the sealing material at the first sidewall of the air gap is in contact with a conductive material of the first conductive interconnect,

the sealing material at the second sidewall of the air gap is in contact with a conductive material of the second conductive interconnect, and

the sealing material at the bottom of the air gap is in contact with an interlayer dielectric (ILD) material of the backend layer.

3. The IC device according to claim 2 , wherein:

the ILD material is a first ILD material,

a second ILD material is at least partially at the first sidewall, the bottom, and the second sidewall of the air gap,

the sealing material at the first sidewall of the air gap is between the conductive material of the first conductive interconnect and the second ILD material at the second sidewall of the air gap,

the sealing material at the second sidewall of the air gap is between the conductive material of the second conductive interconnect and the second ILD material at the second sidewall of the air gap, and

the sealing material at the bottom of the air gap is between the first ILD material and the second ILD material at the bottom of the air gap.

4. The IC device according to claim 3 , wherein:

an etch-stop (ES) material is at least partially at the first sidewall, the bottom, and the second sidewall of the air gap,

the ES material at the first sidewall of the air gap is between the sealing material at the first sidewall of the air gap and the second ILD material at the second sidewall of the air gap,

the ES material at the second sidewall of the air gap is between the sealing material at the second sidewall of the air gap and the second ILD material at the second sidewall of the air gap, and

the ES material at the bottom of the air gap is between the sealing material at the bottom of the air gap and the second ILD material at the bottom of the air gap.

5. The IC device according to claim 2 , wherein:

the conductive material of the first conductive interconnect is a first barrier material, and the first conductive interconnect further includes a first fill material, and

the conductive material of the second conductive interconnect is a second barrier material, and the second conductive interconnect further includes a second fill material.

6. The IC device according to claim 1 , wherein an individual one of the plurality of backend memory cells includes an access transistor and a capacitor.

7. The IC device according to claim 1 , wherein the plurality of conductive interconnects is a plurality of conductive lines.

8. The IC device according to claim 1 , wherein:

an individual pair of the adjacent conductive interconnects with the air gap in between includes a first conductive interconnect and a second conductive interconnect,

a first liner is at least partially at a first sidewall, a bottom, and a second sidewall of the air gap,

the first liner at the bottom of the air gap is in contact with an insulator material of the backend layer,

a second insulator material is at least partially at the first sidewall, the bottom, and the second sidewall of the air gap,

the first liner at the first sidewall of the air gap is between a conductive material of the first conductive interconnect and the second insulator material at the second sidewall of the air gap,

the first liner at the second sidewall of the air gap is between a conductive material of the second conductive interconnect and the second insulator material at the second sidewall of the air gap,

a second liner is at least partially at the first sidewall, the bottom, and the second sidewall of the air gap,

the second liner at the first sidewall of the air gap is between the first liner at the first sidewall of the air gap and the second insulator material at the second sidewall of the air gap,

the second liner at the second sidewall of the air gap is between the first liner at the second sidewall of the air gap and the second insulator material at the second sidewall of the air gap, and

the second liner at the bottom of the air gap is between the first liner at the bottom of the air gap and the second insulator material at the bottom of the air gap.

9. The IC device according to claim 8 , wherein:

a material composition of the second liner is different from a material composition of the first liner.

10. The IC device according to claim 9 , wherein the second liner includes silicon and nitrogen.

11. The IC device according to claim 9 , wherein the second liner is an etch-stop material.

12. The IC device according to claim 9 , wherein:

the first liner at the first sidewall of the air gap is in contact with the conductive material of the first conductive interconnect, and

the first liner at the second sidewall of the air gap is in contact with the conductive material of the second conductive interconnect.

13. The IC device according to claim 1 , further comprising:

a layer of a material comprising silicon and nitrogen on a sidewall and a bottom of the air gap.

14. An integrated circuit (IC) package, comprising:

an IC device; and

a further IC component, coupled to the IC device,

wherein the IC device includes:

a frontend layer with a plurality of frontend transistors, and

a metallization stack over the frontend layer, the metallization stack including:

a backend memory layer with a plurality of memory cells with backend transistors,

a layer with a plurality of conductive lines, wherein the backend memory layer is between the frontend layer and the layer with the plurality of conductive lines, and the plurality of conductive lines includes a first conductive line and a second conductive line,

an air gap between the first conductive line and the second conductive line, and

an etch-stop material at least partially at a first sidewall, a second sidewall, and a bottom of the air gap.

15. The IC package according to claim 14 , wherein the layer with the plurality of conductive lines and with the air gap is at or above a seventh layer of the metallization stack.

16. The IC package according to claim 14 , wherein no memory cells are included in the metallization stack further away from the frontend layer than the layer with the plurality of conductive lines and with the air gap.

17. The IC package according to claim 14 , wherein the metallization stack further includes a sealing material at least partially at the first sidewall, the bottom, and the second sidewall of the air gap, wherein:

the sealing material at the bottom of the air gap is in contact with a first insulator material of the backend layer,

a second insulator material is at least partially at the first sidewall, the bottom, and the second sidewall of the air gap,

the etch-stop material at the first sidewall of the air gap is between the sealing material at the sidewall of the air gap and the second insulator material at the second sidewall of the air gap,

the etch-stop material at the second sidewall of the air gap is between the sealing material at the second sidewall of the air gap and the second insulator material at the second sidewall of the air gap, and

the etch-stop material at the bottom of the air gap is between the sealing material at the bottom of the air gap and the second insulator material at the bottom of the air gap.

18. The IC package according to claim 17 , wherein:

the sealing material at the first sidewall of the air gap is in contact with a conductive material of the first conductive line, and

the sealing material at the second sidewall of the air gap is in contact with a conductive material of the second conductive line.

19. The IC package according to claim 18 , wherein:

the sealing material at the first sidewall of the air gap is between the conductive material of the first conductive line and the second insulator material at the second sidewall of the air gap,

the sealing material at the second sidewall of the air gap is between the conductive material of the second conductive line and the second insulator material at the second sidewall of the air gap, and

the sealing material at the bottom of the air gap is between the first insulator material and the second insulator material at the bottom of the air gap.

20. The IC package according to claim 17 , wherein:

the sealing material at the first sidewall of the air gap is between a conductive material of the first conductive line and the second insulator material at the second sidewall of the air gap,

the sealing material at the second sidewall of the air gap is between a conductive material of the second conductive line and the second insulator material at the second sidewall of the air gap, and

the sealing material at the bottom of the air gap is between the first insulator material and the second insulator material at the bottom of the air gap.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2021
From: SHARMA, ABHISHEK A.; CHEN, ALBERT B.; GOMES, WILFRED; HAMZAOGLU, FATIH; LAJOIE, TRAVIS W.; LE, VAN H.; NIMMAGADDA, ALEKHYA; RESHOTKO, MIRIAM R.; YOO, HUI JAE
To: INTEL CORPORATION
Reel/Frame 056900/0740 →
Continuity (1)
Related Publication 20220406782A1 · Dec 22, 2022
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