IP Library › Granted Patent US 12,598,983
Granted Patent B2
US 12,598,983 · App. 17/524,107 · Granted Apr 7, 2026

Interconnects formed using integrated damascene and subtractive etch processing

Inventors: Nicholas Anthony Lanzillo (Wynantskill, NY); Huai Huang (Clifton Park, NY); Hosadurga Shobha (Niskayuna, NY); Lawrence A. Clevenger (Saratoga Springs, NY)
Assignee: International Business Machines Corporation
H01L23/5283H01L21/76804H01L21/76807H01L21/76885H01L23/5226H01L23/53238H01L23/53295H01L21/76897
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Quick Facts
Patent No.
US 12,598,983
App. No.
17/524,107
Granted
Apr 7, 2026
Kind
B2
Abstract

A semiconductor structure comprises two or more interconnect lines of a first width in a given interconnect level, and two or more interconnect lines of a second width in the given interconnect level. The two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width. The two or more interconnect lines of the first width have sidewalls with a negative taper angle. The two or more interconnect lines of the second width have sidewalls with a positive taper angle.

Claims (40)

1 . A semiconductor structure comprising:

two or more interconnect lines of a first width in a given interconnect level; and

two or more interconnect lines of a second width in the given interconnect level;

wherein the two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width;

wherein the two or more interconnect lines of the first width have sidewalls with a negative taper angle;

wherein the two or more interconnect lines of the second width have sidewalls with a positive taper angle;

wherein the first one of the two or more interconnect lines of the first width comprises a bottom via structure in the given interconnect level that is coincident with bottom portions of each of the two or more interconnect lines of the second width in the given interconnect level; and

wherein the second one of the two or more interconnect lines of the first width comprises a bottom via structure in the given interconnect level that is not coincident with the bottom portions of any of the two or more interconnect lines of the second width in the given interconnect level.

2 . The semiconductor structure of claim 1 , wherein the first width is greater than the second width.

3 . The semiconductor structure of claim 1 , wherein the first width is at least three times greater than the second width.

4 . The semiconductor structure of claim 1 , wherein the two or more interconnect lines of the first width comprise power lines, and wherein the two or more interconnect lines of the second width comprise signal lines.

5 . The semiconductor structure of claim 1 , wherein the two or more interconnect lines of the first width utilize a copper conductor, and wherein the two or more interconnect lines of the second width utilize a non-copper conductor.

6 . The semiconductor structure of claim 1 , wherein the two or more interconnect lines of the first width have respective sidewall profiles that increase in width from bottom to top surfaces thereof, and wherein the two or more interconnect lines of the second width have respective sidewall profiles that decrease in width from bottom to top surfaces thereof.

7 . The semiconductor structure of claim 1 , wherein the two or more interconnect lines of the first width have damascene sidewall profiles, and wherein the two or more interconnect lines of the second width have subtractive-etch sidewall profiles.

8 . The semiconductor structure of claim 1 , wherein at least one of the two or more interconnect lines of the second width comprises a top via structure in the given interconnect level coincident with top portions of the two or more interconnect lines of the first width.

9 . The semiconductor structure of claim 1 , wherein the two or more interconnect lines of the first width comprise via structures in the given interconnect level located below the two or more interconnect lines of the first width, and wherein the two or more interconnect lines of the second width comprise via structures in the given interconnect level located above the two or more interconnect lines of the second width.

10 . The semiconductor structure of claim 1 , further comprising:

an interlevel dielectric layer surrounding the two or more interconnect lines of the first width and the two or more interconnect lines of the second width; and

a dielectric capping layer disposed over the interlevel dielectric layer.

11 . The semiconductor structure of claim 10 , further comprising at least one additional interconnect level disposed above the given interconnect level, and wherein the at least one additional interconnect level comprises one or more interconnect lines with a dual damascene profile that contact at least one of one or more of the interconnect lines of the first width and one or more of the interconnect lines of the second width through via structures disposed through the dielectric capping layer.

12 . The semiconductor structure of claim 10 , further comprising at least one additional interconnect level disposed above the given interconnect level, and wherein the at least one additional interconnect level comprises one or more interconnect lines with a damascene profile disposed through the dielectric capping layer which directly contact at least one of: one or more of the interconnect lines of the first width; and one or more top via structures in the given interconnect level that are located above one or more of the two or more interconnect lines of the second width.

13 . An integrated circuit, comprising: a back-end-of-line interconnect structure comprising two or more interconnect levels; wherein at least a given one of the two or more interconnect levels comprises:

two or more interconnect lines of a first width; and

two or more interconnect lines of a second width;

wherein the two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width; wherein the two or more interconnect lines of the first width have sidewalls with a negative taper angle; wherein the two or more interconnect lines of the second width have sidewalls with a positive taper angle; wherein the first one of the two or more interconnect lines of the first width comprises a bottom via structure in the given interconnect level that is coincident with bottom portions of each of the two or more interconnect lines of the second width in the given interconnect level; and

wherein the second one of the two or more interconnect lines of the first width comprises a bottom via structure in the given interconnect level that is not coincident with the bottom portions of any of the two or more interconnect lines of the second width in the given interconnect level.

14 . The integrated circuit of claim 13 , wherein the first width is greater than the second width.

15 . The integrated circuit of claim 13 , wherein the two or more interconnect lines of the first width utilize a copper conductor, and wherein the two or more interconnect lines of the second width utilize a non-copper conductor.

16 . The integrated circuit of claim 13 , wherein the two or more interconnect lines of the first width comprise via structures in the given interconnect level located below the two or more interconnect lines of the first width, and wherein the two or more interconnect lines of the second width comprise via structures in the given interconnect level located above the two or more interconnect lines of the second width.

17 . A method comprising:

forming two or more interconnect lines of a first width in a given interconnect level; and

forming two or more interconnect lines of a second width in the given interconnect level;

wherein the two or more interconnect lines of the second width are disposed between a first one of the two or more interconnect lines of the first width and a second one of the two or more interconnect lines of the second width;

wherein the two or more interconnect lines of the first width have sidewalls with a negative taper angle;

wherein the two or more interconnect lines of the second width have sidewalls with a positive taper angle;

wherein the first one of the two or more interconnect lines of the first width comprises a bottom via structure in the given interconnect level that is coincident with bottom portions of each of the two or more interconnect lines of the second width in the given interconnect level; and

wherein the second one of the two or more interconnect lines of the first width comprises a bottom via structure in the given interconnect level that is not coincident with the bottom portions of any of the two or more interconnect lines of the second width in the given interconnect level.

18 . The method of claim 17 , wherein the first width is greater than the second width.

19 . The method of claim 17 , wherein the two or more interconnect lines of the first width are formed using damascene processing, and wherein the two or more interconnect lines of the second width are formed using subtractive etch processing.

20 . The method of claim 17 , wherein at least one of the two or more interconnect lines of the second width comprises a top via structure in the given interconnect level coincident with top portions of the two or more interconnect lines of the first width.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 11, 2021
From: LANZILLO, NICHOLAS ANTHONY; HUANG, HUAI; SHOBHA, HOSADURGA; CLEVENGER, LAWRENCE A.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 058085/0956 →
Continuity (1)
Related Publication 20230146512A1 · May 11, 2023
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