IP Library › Granted Patent US 12,225,720
Granted Patent B2
US 12,225,720 · App. 17/530,861 · Granted Feb 11, 2025

Three-dimensional memory device with doped semiconductor bridge structures and methods for forming the same

Inventors: Ryousuke Itou (Yokkaichi, JP); Akihisa Sai (Yokkaichi, JP); Kenzo Iizuka (Yokkaichi, JP)
Assignee: SANDISK TECHNOLOGIES LLC
H10B41/27H01L21/32134H01L21/76877H10B41/10H10B43/10H10B43/27H01L23/5221H01L23/53271
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Quick Facts
Patent No.
US 12,225,720
App. No.
17/530,861
Granted
Feb 11, 2025
Kind
B2
Abstract

A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate, and memory opening fill structures including vertical stacks of memory elements are formed through the vertically alternating sequence. Backside trenches are formed to divide the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers. Bridge structures are formed within each of the backside trenches. The sacrificial material layers are replaced with electrically conductive layers while the bridge structure are present within the backside trenches.

Claims (25)

1. A three-dimensional memory device, comprising:

a pair of alternating stacks of insulating layers and electrically conductive layers laterally spaced apart from each other by a backside trench, wherein each of the pair of alternating stacks and the backside trench laterally extend along a first horizontal direction;

arrays of memory openings vertically extending through a respective alternating stack among the pair of alternating stacks;

arrays of memory openings fill structures located in the arrays of memory openings, wherein each of the memory opening fill structures comprises a respective vertical stack of memory elements; and

a backside trench fill structure located within the backside trench and comprising a plurality of bridge structures;

wherein each of the plurality of bridge structures includes a doped semiconductor material; and

wherein each of the plurality of bridge structures is embedded within a respective dielectric semiconductor oxide liner which comprises a dielectric oxide of the doped semiconductor material.

2. The three-dimensional memory device of claim 1 , wherein the plurality of bridge structures comprises:

a first bridge structure located at a first vertical distance from a horizontal plane including a top surface of the substrate; and

a second bridge structure located at a second vertical distance from the horizontal plane, wherein the second vertical distance is different from the first vertical distance.

3. The three-dimensional memory device of claim 2 , wherein the second bridge structure is laterally offset from the first bridge structure along the first horizontal direction.

4. The three-dimensional memory device of claim 2 , wherein the second bridge structure does not have any areal overlap with the first bridge structure in a plan view along a vertical direction that is perpendicular to a top surface of the substrate.

5. The three-dimensional memory device of claim 1 , wherein:

the first bridge structure is located above a horizontal plane including topmost surfaces of the pair of alternating stacks; and

the second bridge structure is located below the horizontal plane including the topmost surfaces of the pair of alternating stacks.

6. The three-dimensional memory device of claim 5 , further comprising a pair of contact-level dielectric material portions located above a respective alternating stack within the pair of alternating stacks, wherein the first bridge structure has a top surface located within a horizontal plane including top surfaces of the pair of contact-level dielectric material portions.

7. The three-dimensional memory device of claim 1 , wherein the doped semiconductor material comprises boron doped silicon.

8. The three-dimensional memory device of claim 1 , wherein the plurality of bridge structures comprises three bridge structures located at three different vertical distances from a horizontal plane including a top surface of the substrate.

9. The three-dimensional memory device of claim 1 , wherein the backside trench fill structure comprises an insulating backside trench fill material portion embedding each bridge structure of the plurality of bridge structures.

10. The three-dimensional memory device of claim 9 , wherein:

the backside trench fill structure contacts a respective sidewall of each layer within the pair of alternating stacks; and

sidewalls of the insulating backside trench fill material portion contacts a pair of lengthwise sidewalls of the backside trench that laterally extends along the first horizontal direction.

11. The three-dimensional memory device of claim 1 , wherein the plurality of bridge structures comprises:

a row of first bridge structures that are arranged along the first horizontal direction and located at a first vertical distance from a horizontal plane including a top surface of the substrate; and

a row of second bridge structures that are arranged along the first horizontal direction and located at a second vertical distance from the horizontal plane, wherein the second vertical distance is different from the first vertical distance.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 19, 2021
From: ITOU, RYOUSUKE; SAI, AKIHISA; IIZUKA, KENZO
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 058164/0259 →
Continuity (2)
Continuation In Part 17406463 · Aug 19, 2021
Related Publication 20230055230A1 · Feb 23, 2023
References Cited (29)
US 9679906B2 · Lu et al. · 2017 [cited by applicant]
US 20150318301A1 · Lee · 2015 [cited by examiner]
US 20170047334A1 · Lu · 2017 [cited by examiner]
US 20190115356A1 · Lee · 2019 [cited by applicant]
US 20200395376A1 · Huo · 2020 [cited by examiner]
US 20210036004A1 · Moriyama et al. · 2021 [cited by applicant]
US 20210057336A1 · Shao et al. · 2021 [cited by applicant]
US 20210057428A1 · Hu et al. · 2021 [cited by applicant]
US 20210111064A1 · Billingsley et al. · 2021 [cited by applicant]
US 20210125920A1 · Hu · 2021 [cited by examiner]
US 20210134827A1 · Iwai et al. · 2021 [cited by applicant]
US 20210202324A1 · Scarbrough · 2021 [cited by examiner]
US 20220085057A1 · Jang · 2022 [cited by examiner]
US 20220189982A1 · Luo · 2022 [cited by examiner]
US 20220238548A1 · Liu et al. · 2022 [cited by applicant]
Endoh et al., “Novel Ultra High Density Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. [cited by applicant]
U.S. Appl. No. 16/782,307, filed Feb. 5, 2020, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 16/881,346, filed May 22, 2020, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 16/881,401, filed May 22, 2020, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/039,160, filed Sep. 30, 2020, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/116,093, filed Dec. 9, 2020, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/146,866, filed Jan. 12, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/174,064, filed Feb. 11, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/174,094, filed Feb. 11, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/226,321, filed Apr. 9, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/376,490, filed Jul. 15, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/406,463, filed Aug. 19, 2021, SanDisk Technologies LLC. [cited by applicant]
Notification of Transmittal of The International Search Report and Written Opinion of the International Searching Authority for International Patent Application No. PCT/US2022/028391, mailed Sep. 21, 2022, 13 pages. [cited by applicant]
USPTO Office Communication, Non-Final Office Action for U.S. Appl. No. 17/406,463, mailed Apr. 23, 2024, 14 pages. [cited by applicant]