Memory devices having vertical transistors and methods for forming the same
In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells, and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with a plurality of sides of the semiconductor body. One end of the semiconductor body coupled to the storage unit is flush with the gate structure. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.
1. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit;
a second semiconductor structure comprising:
an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor,
wherein the vertical transistor comprises a semiconductor body extending in the first direction and a gate structure in contact with a plurality of sides of the semiconductor body, and one end of the semiconductor body coupled to the storage unit is flush with a gate electrode of the gate structure in a plane perpendicular to the first direction, at a first side of the second semiconductor structure, electrodes of part of the storage units being connected to extend in a second direction perpendicular to the first direction; and
a plurality of bit lines coupled to the vertical transistors of the memory cells and each extending in the second direction, wherein a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the vertical transistors in the first direction, the vertical transistors being arranged between the bit lines and the storage units; and
at a second side of the second semiconductor structure opposite the first side, a bonding interface arranged between the first semiconductor structure and the second semiconductor structure in the first direction, wherein the array of memory cells is coupled to the peripheral circuit across the bonding interface.
2. The 3D memory device of claim 1 , wherein the second semiconductor structure further comprises a plurality of word lines each extending in a third direction perpendicular to the first direction and the second direction.
3. The 3D memory device of claim 2 , wherein the gate structure comprises the gate electrode, and a gate dielectric between the gate electrode and the semiconductor body in the second and third directions.
4. The 3D memory device of claim 3 , wherein the one end of the semiconductor body is flush with a top surface of the gate electrode, the one end of the semiconductor body not extending beyond the top surface of the gate electrode in the first direction.
5. The 3D memory device of claim 3 , wherein the gate dielectrics of two adjacent vertical transistors of the vertical transistors in the third direction are separate.
6. The 3D memory device of claim 1 , wherein the vertical transistor is a gate-all-around (GAA) transistor in which the gate structure fully circumscribes the semiconductor body in a plan view.
7. The 3D memory device of claim 1 , wherein the vertical transistor is a tri-gate transistor in which the gate structure partially circumscribes the semiconductor body in a plan view.
8. The 3D memory device of claim 1 , wherein the vertical transistor further comprises a source and a drain disposed at two ends of the semiconductor body, respectively, in the first direction.
9. The 3D memory device of claim 8 , wherein
one of the source and the drain of the vertical transistor is coupled to the storage unit in a respective memory cell; and
another one of the source and the drain of the vertical transistor is coupled to the respective bit line.
10. The 3D memory device of claim 1 , wherein the bit lines are disposed between the vertical transistors and the bonding interface.
11. A three-dimensional (3D) memory device, comprising:
a first semiconductor structure comprising a peripheral circuit;
a second semiconductor structure comprising:
an array of memory cells, each of the memory cells comprising a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor, wherein the storage unit comprises an electrode in direct contact with an end of the vertical transistor;
a plurality of bit lines coupled to the vertical transistors of the memory cells and each extending in a second direction perpendicular to the first direction, the vertical transistors being arranged between the bit lines and the storage units;
a plurality of word lines coupled to the memory cells and each extending in a third direction perpendicular to the first direction and the second direction; and
a first dielectric layer, a second dielectric layer, and a third dielectric layer having a material different from the first and second dielectric layers, the storage unit being formed in the third dielectric layer, wherein the word lines are sandwiched between the first and second dielectric layers in the first direction, and the first and second dielectric layers are arranged between the third dielectric layer and the bit lines, and a semiconductor body of the vertical transistor extends through the first dielectric layer and the second dielectric layer that extend laterally in the second direction, respectively; and
at a side of the plurality of bit lines of the second semiconductor structure, a bonding interface arranged between the first semiconductor structure and the second semiconductor structure in the first direction, wherein the array of memory cells is coupled to the peripheral circuit across the bonding interface.
12. The 3D memory device of claim 11 , wherein
the vertical transistor comprises a semiconductor body extending in the first direction and a gate structure in contact with a plurality of sides of the semiconductor body; and
two ends of the semiconductor body in the first direction extend beyond the gate structure, respectively.
13. The 3D memory device of claim 11 , wherein a respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the vertical transistors in the first direction.
14. The 3D memory device of claim 12 , wherein the gate structure comprises a gate electrode, and a gate dielectric between the gate electrode and the semiconductor body in the second and third directions.
15. The 3D memory device of claim 11 , wherein the first and second dielectric layers comprise silicon nitride, and the third dielectric layer comprises silicon oxide.
16. The 3D memory device of claim 12 , wherein the vertical transistor is a gate-all-around (GAA) transistor in which the gate structure fully circumscribes the semiconductor body in a plan view.
17. The 3D memory device of claim 12 , wherein the vertical transistor is a tri-gate transistor in which the gate structure partially circumscribes the semiconductor body in a plan view.
18. The 3D memory device of claim 12 , wherein the vertical transistor further comprises a source and a drain disposed at two ends of the semiconductor body, respectively, in the first direction.
19. The 3D memory device of claim 18 , wherein
one of the source and the drain of the vertical transistor is coupled to the storage unit in a respective memory cell; and
another one of the source and the drain of the vertical transistor is coupled to the respective bit line.
20. The 3D memory device of claim 11 , wherein the bit lines are disposed between the vertical transistors and the bonding interface.