IP Library Granted Patent US 12,249,574
Granted Patent B2
US 12,249,574 · App. 17/576,137 · Granted Mar 11, 2025

Interconnect structure of semiconductor device and method of forming same

Inventors: Tung Ying Lee (Hsinchu, TW); Bo-Jiun Lin (Jhubei, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L23/5226H01L21/76843H01L21/76877H01L23/53238H01L23/53266
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Quick Facts
Patent No.
US 12,249,574
App. No.
17/576,137
Granted
Mar 11, 2025
Kind
B2
Abstract

A device includes a substrate, a dielectric layer over the substrate, and a conductive interconnect in the dielectric layer. The conductive interconnect includes a barrier/adhesion layer and a conductive layer over the barrier/adhesion layer. The barrier/adhesion layer includes a material having a chemical formula MX n , with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2.

Claims (53)

1. A method comprising:

forming a dielectric layer over a substrate;

patterning the dielectric layer to form an opening in the dielectric layer;

forming a barrier/adhesion layer along a bottom and sidewalls of the opening, a material of the barrier/adhesion layer having a chemical formula MX n , with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2, wherein forming the barrier/adhesion layer comprises:

depositing a layer of the transition metal element along the bottom and the sidewalls of the opening; and

after depositing the layer of the transition metal element, performing a chalcogen treatment on the layer of the transition metal element; and

depositing a conductive layer over the barrier/adhesion layer in the opening.

2. The method of claim 1 , wherein depositing the layer of the transition metal element comprises performing a physical vapor deposition (PVD) process.

3. The method of claim 1 , wherein performing the chalcogen treatment comprises performing a plasma enhanced chemical deposition (PECVD) process using a precursor comprising the chalcogen element.

4. The method of claim 1 , wherein depositing the conductive layer comprises depositing a seed layer over the barrier/adhesion layer in the opening, the seed layer filling the opening.

5. The method of claim 1 , wherein depositing the conductive layer comprises:

depositing a seed layer over the barrier/adhesion layer in the opening; and

depositing a conductive fill material over the seed layer in the opening, the conductive fill material filling the opening.

6. The method of claim 1 , wherein the barrier/adhesion layer comprises a plurality of sub-layers.

7. A method comprising:

forming a first dielectric layer over a substrate, the first dielectric layer having a recess;

forming a conductive via in the recess in the first dielectric layer, forming the conductive via comprising:

forming a first barrier/adhesion layer comprising a first material, the first material having a chemical formula MX n , with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2; and

forming a first conductive layer over the first barrier/adhesion layer;

forming a second dielectric layer over the first dielectric layer and the conductive via; and

forming a conductive line in the second dielectric layer, forming the conductive line comprising:

forming a second barrier/adhesion layer comprising the first material; and

forming a second conductive layer over the second barrier/adhesion layer.

8. The method of claim 7 , wherein forming the first barrier/adhesion layer comprises:

depositing a layer of the transition metal element along a bottom and sidewalls of the recess; and

after depositing the layer of the transition metal element, performing a chalcogen treatment on the layer of the transition metal element.

9. The method of claim 7 , wherein forming the first barrier/adhesion layer comprises:

depositing the first barrier/adhesion layer using a deposition process, the deposition process performed using a metal-containing precursor and a chalcogen-containing precursor.

10. The method of claim 7 , wherein the first barrier/adhesion layer has a layered structure.

11. The method of claim 7 , wherein forming the conductive via further comprises:

forming a first seed layer over the first barrier/adhesion layer, the first seed layer being an uppermost layer of the conductive via.

12. The method of claim 7 , wherein forming the first conductive layer comprises:

forming a first seed layer over the first barrier/adhesion layer; and

forming a first conductive fill layer over the first seed layer, a top surface of the first conductive fill layer being level with a top surface of the first dielectric layer.

13. The method of claim 7 , wherein forming the second conductive layer comprises:

forming a second seed layer over the second barrier/adhesion layer, the second seed layer being an uppermost layer of the conductive line.

14. The method of claim 7 , wherein forming the second conductive layer comprises:

forming a second seed layer over the second barrier/adhesion layer; and

forming a second conductive fill layer over the second seed layer, a top surface of the second conductive fill layer being level with a top surface of the second dielectric layer.

15. The method of claim 7 , wherein the second barrier/adhesion layer is in physical contact with the first conductive layer.

16. A method comprising:

forming a first dielectric layer over a substrate;

patterning the first dielectric layer to form a via opening in the first dielectric layer;

depositing a barrier/adhesion layer along a bottom and sidewalls of the via opening using a first deposition process, the first deposition process using a metal-containing precursor and a chalcogen-containing precursor, a material of the barrier/adhesion layer having a chemical formula MX n , with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2;

depositing a conductive layer over the barrier/adhesion layer in the via opening;

depositing a second dielectric layer over the first dielectric layer and the conductive layer; and

forming a conductive line in the second dielectric layer, wherein the conductive line contacts the conductive layer.

17. The method of claim 16 , wherein the barrier/adhesion layer has a plurality of sub-layers, wherein each of the sub-layers has a thickness in a range of 0.5 nm and 1 nm.

18. The method of claim 16 , wherein the metal-containing precursor comprises pentakis (dimethylamino) tantalum (V), tantalum ethoxide, or tantalum chloride, wherein the chalcogen-containing precursor comprises dimethyl disulfide or H 2 S.

19. The method of claim 16 , wherein the barrier/adhesion layer has a plurality of wavy sub-layers.

20. The method of claim 1 , wherein the conductive layer is part of a conductive via, further comprising:

depositing another dielectric layer over the dielectric layer and the conductive via; and

forming a conductive line in the another dielectric layer, wherein the conductive line contacts the conductive via.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 14, 2022
From: LEE, TUNG YING; LIN, BO-JIUN
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 058660/0584 →
Continuity (3)
Provisional Application 63226843 · Jul 29, 2021
Provisional Application 63214276 · Jun 24, 2021
Related Publication 20220415785A1 · Dec 29, 2022
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